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LRS1383C 1D44D PJS6815 BA9741F 07005 LTC2271 2SA1209T BU2525A
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  march 2009 rev 7 1/193 1 st72324bxx 8-bit mcu, 3.8 to 5.5 v operating range with 8 to 32 kbyte flash/rom, 10-bit adc, 4 timers, spi, sci features memories 8 to 32 kbyte dual voltage high density flash (hdflash) or rom with readout protection capability. in-applicati on programming and in- circuit programming for hdflash devices 384 bytes to 1 kbyte ram hdflash endurance: 1 kcycle at 55 c, data retention 40 years at 85 c clock, reset and supply management enhanced low voltage supervisor (lvd) with programmable reset thre sholds and auxiliary voltage detector (avd) wi th interrup t capability clock sources: crysta l/ceramic resonator oscillators, int. rc osc. and ext. clock input pll for 2x frequency multiplication 4 power saving modes: slow, wait, active-halt, and halt interrupt management nested interrupt controlle r. 10 interrupt vectors plus trap and reset. 9/6 ext. interrupt lines (on 4 vectors) up to 32 i/o ports 32/24 multifunctional bidirectional i/os, 22/17 alternate function lines, 12/10 high sink outputs 4 timers main clock controller with real-time base, beep and clock-out capabilities configurable watchdog timer 16-bit timer a with 1 input capture, 1 output compare, ext. clock input, pwm and pulse generator modes 16-bit timer b with 2 input captures, 2 output compares, pwm and pulse generator modes 2 communication interfaces spi synchronous serial interface sci asynchronous serial interface 1 analog peripheral (low current coupling) 10-bit adc with up to 12 input ports development tools in-circuit test ing capability lqfp44 10 x 10 lqfp32 7 x 7 sdip42 600 mil sdip32 400 mil table 1. device summary device memory ram (stack) volta ge range temp. range package st72324bk2 flash/rom 8 kbytes 384 (256) bytes 3.8 to 5.5 v up to -40 to 125 c lqfp32 7x7/ sdip32 st72324bk4 flash/rom 16 kbytes 512 (256) bytes st72324bk6 flash/rom 32 kbytes 1024 (256) bytes st72324bj2 flash/rom 8 kbytes 384 (256) bytes lqfp44 10x10/ sdip42 st72324bj4 flash/rom 16 kbytes 512 (256) bytes st72324bj6 flash/rom 32 kbytes 1024 (256) bytes www.st.com
contents st72324bxx 2/193 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.1 readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7.1 flash control/status register (fcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 central processing unit (cpu ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.2 index registers (x and y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.3 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.4 condition code register (cc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.5 stack pointer register (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 pll (phase locked loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.2 crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
st72324bxx contents 3/193 6.3.3 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.1 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5.1 lvd (low voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5.2 avd (auxiliary voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5.3 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.5.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6 si registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.6.1 system integrity (si) control/status register (sicsr) . . . . . . . . . . . . . . . 39 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2.1 servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.2 different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.3 non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.4 maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4 concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5.1 cpu cc register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5.2 interrupt software priority registers (isprx) . . . . . . . . . . . . . . . . . . . . . . 46 7.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.2 external interrupt control register (eicr) . . . . . . . . . . . . . . . . . . . . . . . . 49 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.4.1 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.4.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
contents st72324bxx 4/193 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.5.1 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1.4 how to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.1.6 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.1.7 using halt mode with the wdg (wdghalt option) . . . . . . . . . . . . . . . 68 10.1.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.1.9 control register (wdgcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.2 main clock controller with real-time clock and beeper (mcc/rtc) . . . . . 69 10.2.1 programmable cpu clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.2.2 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.3 real-time clock (rtc) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.4 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.2.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.2.7 mcc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.3.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
st72324bxx contents 5/193 10.3.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.4.4 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.4.5 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.4.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.4.8 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.5 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.5.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.5.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.5.7 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.6 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.6.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.6.6 adc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 11.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
contents st72324bxx 6/193 12 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.2.1 voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.2.2 current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.4 lvd/avd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.4.1 operating conditions with lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.4.2 auxiliary voltage detector (avd) thresholds . . . . . . . . . . . . . . . . . . . . . 145 12.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.1 rom current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.2 flash current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.5.3 supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.5.4 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.6 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.6.1 general timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.6.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.6.3 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 150 12.6.4 rc oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12.6.5 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.7 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.7.1 ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.7.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.8 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.8.1 functional electr omagnetic susceptibility (ems) . . . . . . . . . . . . . . . . . 155 12.8.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.8.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 157 12.9 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.9.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.9.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
st72324bxx contents 7/193 12.10 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.10.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.10.2 iccsel/vpp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.11 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.11.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.12 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 166 12.12.1 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.13 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.13.1 analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 170 12.13.2 general pcb design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 12.13.3 adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.1 ecopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.2.1 lqfp44 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.2.2 sdip42 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.2.3 lqfp32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.2.4 sdip32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14 device configuration and ordering informati on . . . . . . . . . . . . . . . . . 178 14.1 flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 14.1.1 flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 14.2 rom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.2.1 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.2 evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.3 development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.4 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3.5 socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 184 14.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1 all flash and rom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
contents st72324bxx 8/193 15.1.1 safe connection of osc1/osc2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1.2 external interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1.3 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.1.4 clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 187 15.1.5 16-bit timer pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.1.6 timd set simultaneously with oc interrupt . . . . . . . . . . . . . . . . . . . . . 188 15.1.7 sci wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.2 8/16 kbyte flash devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.2.1 39-pulse icc entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.2.2 negative current injection on pin pb0 . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.3 8/16 kbyte rom devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.3.1 readout protection with lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.3.2 i/o port a and f configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
st72324bxx list of tables 9/193 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3. hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. sectors available in flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5. flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6. arithmetic management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. software interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. interrupt software priority selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. st7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. effect of low power modes on si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. avd interrupt control/ wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 table 12. sicsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13. reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14. interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15. cpu cc register interrupt bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 table 16. interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 17. isprx interrupt vector correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 18. dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 19. eicr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 20. interrupt sensitivity - ei2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 21. interrupt sensitivity - ei3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 22. interrupt sensitivity - ei0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 23. interrupt sensitivity - ei1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 24. nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 25. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 26. mcc/rtc low power mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 27. dr register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 28. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 29. i/o port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 30. effect of low power modes on i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 table 31. i/o port interrupt cont rol/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table 32. port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 33. i/o port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 34. effect of lower power modes on watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 35. wdgcr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 36. watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 37. effect of low power modes on mcc/rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 38. mcc/rtc interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 39. mccsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 40. time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 41. mccbcr register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 42. beep frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 43. main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 44. input capture byte distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 45. output compare byte distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 46. effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 47. 16-bit timer interrupt control/wa keup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 48. summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
list of tables st72324bxx 10/193 table 49. cr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 50. cr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 51. csr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 52. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 53. effect of low power modes on spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 table 54. spi interrupt control/ wakeup capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 table 55. spicr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 56. spi master mode sck frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 57. spicsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 58. spi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 59. frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 60. effect of low power modes on sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 20 table 61. sci interrupt c ontrol/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 0 table 62. scisr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 63. scicr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 64. scicr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 65. scibrr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 66. scierpr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 67. scietpr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 68. baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 69. sci register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 27 table 70. effect of low power modes on adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 71. adccsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 72. adcdrh register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 73. adcdrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 74. adc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 table 75. addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 76. cpu addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 77. inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 78. immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 79. instructions supporting direct, indexed, indirect and indirect indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 table 80. relative direct and indirect instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 81. instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 82. instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 83. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 84. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 85. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 86. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 87. operating conditions with lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 88. avd thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 89. rom current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 90. flash current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 91. oscillators, pll and lvd current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 92. on-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 93. general timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 94. external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 95. crystal and ceramic resonator oscillators (8/16 kbyte flash and rom devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 96. crystal and ceramic resona tor oscillators (32 kbyte flash and rom devices) . . . . . . . . 151 table 97. oscrange selection for typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 98. rc oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
st72324bxx list of tables 11/193 table 99. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 100. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 101. dual voltage hdflash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 102. ems test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 103. emi emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 104. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 105. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 106. general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 107. output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 108. asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 109. iccsel/v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 110. 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 111. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 112. 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 113. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 114. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 115. 42-pin dual in line package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 116. 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 117. 32-pin dual in-line package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 118. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 119. flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 120. option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 121. option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 122. package selection (opt7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 123. stmicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 124. suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 125. port a and f configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 126. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
list of figures st72324bxx 12/193 list of figures figure 1. device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. 44-pin lqfp package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. 42-pin sdip package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. 32-pin lqfp package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. 32-pin sdip package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 8. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11. pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12. clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 13. reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 17. using the avd to monitor v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 18. interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 19. priority decision process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20. concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21. nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 22. external interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 23. power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 24. slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 25. wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 26. active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 27. active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 28. halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 29. halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 30. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 31. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 32. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 33. approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 34. exact timeout duration (t min and t max ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 35. main clock controller (mcc/rtc) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 36. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 37. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 38. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 39. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 40. counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 41. input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 42. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 43. output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 44. output compare timing diagram, f timer =f cpu /2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 45. output compare timing diagram, f timer =f cpu /4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 46. one pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 47. one pulse mode timing example(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 figure 48. pulse width modulation mode timing example with two output compare functions(1)(2) . . 86
st72324bxx list of figures 13/193 figure 49. pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 50. serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 51. single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 52. generic ss timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 53. hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 54. data clock timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 55. clearing the wcol bit (wri te collision flag) software sequence . . . . . . . . . . . . . . . . . . . 103 figure 56. single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 57. sci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 58. word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 59. sci baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 60. bit sampling in reception mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 61. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 62. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 63. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 64. f cpu max versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 65. typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 66. typical application with a crystal or ceramic resonator (8/16 kbyte flash and rom devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1 figure 67. typical application with a crystal or ceramic resonator (32 kbyte flash and rom devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 figure 68. typical f osc(rcint) vs t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 69. integrated pll jitter vs signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 figure 70. unused i/o pins configured as input(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 figure 71. typical i pu vs. v dd with v in = v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 72. typical v ol at v dd = 5 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 73. typical v ol at v dd = 5 v (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 74. typical v oh at v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 75. typical v ol vs. v dd (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 76. typical v ol vs. v dd (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 77. typical v oh vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 78. reset pin protection when lvd is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 79. reset pin protection when lvd is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 80. two typical applications with iccsel/v pp pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 81. spi slave timing diagram with cpha = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 82. spi slave timing diagram with cpha = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 83. spi master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 84. r ain max. vs f adc with c ain = 0 pf(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 85. recommended c ain and r ain values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 86. typical a/d converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 87. power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 88. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 89. 44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2 figure 90. 42-pin plastic dual in-line package, shrink 600-mil width . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 91. 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 figure 92. 32-pin plastic dual in-line package, shrink 400-mil width . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 93. st72324bxx ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
description st72324bxx 14/193 1 description the st72324bxx devices are members of the st7 microcontroller family designed for mid- range applications running from 3.8 to 5.5 v. different package options offer up to 32 i/o pins. all devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with flash or rom program memory. the st7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code. the on-chip peripherals include an a/d converter, two general purpose timers, an spi interface and an sci interface. for power economy, the microcontroller can switch dynamically into, slow, wait, active-halt or ha lt mode when the application is in idle or stand-by state. typical applications include consumer, home, office and industrial products. figure 1. device block diagram 8-bit core alu address and data bus osc1 v pp control program (8 - 32 kbytes) v dd reset port f pf7:6, 4, 2:0 timer a beep port a ram (384 - 1024 bytes) port c 10-bit adc v aref v ssa port b pb4:0 port e pe1:0 (2 bits) sci timer b pa7:3 (5 bits on j devices) port d pd5:0 spi pc7:0 (8 bits) v ss watchdog osc lv d osc2 memory mcc/rtc/beep (4 bits on k devices) (5 bits on j devices) (3 bits on k devices) (6 bits on j devices) (2 bits on k devices) (6 bits on j devices) (5 bits on k devices)
st72324bxx pin description 15/193 2 pin description figure 2. 44-pin lqfp package pinout figure 3. 42-pin sdip package pinout mco/ain8/pf0 beep/(hs) pf1 (hs) pf2 ocmp1_a/ain10/pf4 icap1_a/(hs) pf6 extclk_a/(hs) pf7 v dd_0 v ss_0 ain5/pd5 v aref v ssa 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei2 ei3 ei0 ei1 pb3 (hs) pb4 ain0/pd0 ain1/pd1 ain2/pd2 ain3/pd3 ain4/pd4 rdi / pe1 pb0 pb1 pb2 pc6/sck/iccclk pc5/mosi/ain14 pc4 / miso/iccdata pc3 (hs)/icap1_b pc2 (hs)/icap2_b pc1/ocmp1_b/ain13 pc0/ocmp2_b/ain12 v ss_1 v dd_1 pa 3 ( h s ) pc7/ss /ain15 v ss _ 2 reset v pp /iccsel pa 7 ( h s ) pa 6 ( h s ) pa 5 ( h s ) pa 4 ( h s ) pe0/tdo v dd _ 2 osc1 osc2 eix associated external interrupt vector (hs) 20 ma high sink capability 38 37 36 35 34 33 32 31 30 29 28 27 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 39 40 41 42 (hs) pb4 ain0 / pd0 ain12 / ocmp2_b / pc0 extclk_a / (hs) pf7 icap1_a / (hs) pf6 ain10 / ocmp1_a / pf4 (hs) pf2 beep / (hs) pf1 mco / ain8 / pf0 ain5 / pd5 ain4 / pd4 ain3 / pd3 ain2 / pd2 ain1 / pd1 v ssa v aref pb3 pb2 pa4 (hs) pa5 (hs) pa6 (hs) pa7 (hs) v pp / iccsel reset v ss _2 v dd _2 pe0 / tdo pe1 / rdi pb0 pb1 osc1 osc2 ei3 ei0 ei2 ei1 21 20 17 18 19 ain14 / mosi / pc5 iccdata / miso / pc4 icap1_b / (hs) pc3 icap2_b/ (hs) pc2 ain13 / ocmp1_b / pc1 26 25 24 23 22 pc6 / sck / iccclk pc7 / ss / ain15 pa3 (hs) v dd_1 v ss_1 eix associated external interrupt vector (hs) 20 ma high sink capability
pin description st72324bxx 16/193 figure 4. 32-pin lqfp package pinout figure 5. 32-pin sdip package pinout see section 12: electrical characteristics on page 141 for external pin connection guidelines. refer to section 9: i/o ports on page 58 for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. iccdata/miso/pc4 ain14/mosi/pc5 iccclk/sck/pc6 ain15/ss /pc7 (hs) pa3 ain13/ocmp1_b/pc1 icap2_b/(hs) pc2 icap1_b/(hs) pc3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 101112131415 16 1 2 3 4 5 6 7 8 ei1 ei3 ei0 ocmp1_a/ain10/pf4 icap1_a/(hs) pf6 extclk_a/(hs) pf7 ain12/ocmp2_b/pc0 v aref v ssa mco/ain8/pf0 beep/(hs) pf1 v pp /iccsel pa 7 ( h s ) pa 6 ( h s ) pa 4 ( h s ) osc1 osc2 v ss _ 2 reset pb0 pe1/rdi pe0/tdo v dd _ 2 pd1/ain1 pd0/ain0 pb4 (hs) pb3 ei2 eix associated external interrupt vector (hs) 20 ma high sink capability 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 (hs) pb4 ain0 / pd0 ain14 / mosi / pc5 iccdata/ miso / pc4 icap1_b / (hs) pc3 icap2_b / (hs) pc2 ain13 / ocmp1_b / pc1 ain12 / ocmp2_b / pc0 extclk_a / (hs) pf7 beep / (hs) pf1 mco / ain8 / pf0 v ssa v aref ain1 / pd1 icap1_a / (hs) pf6 ocmp1_a / ain10 / pf4 pb3 pb0 pc6 / sck / iccclk pc7 / ss / ain15 pa 3 ( h s ) pa 4 ( h s ) pa 6 ( h s ) pa 7 ( h s ) v pp / iccsel osc2 osc1 v dd_2 pe0 / tdo pe1 / rdi v ss_2 reset ei0 ei3 ei2 ei1 eix associated external interrupt vector (hs) 20ma high sink capability
st72324bxx pin description 17/193 legend / abbreviations for ta b l e 2 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7 dd c t = cmos 0.3v dd /0.7 dd with input trigger output level: hs = 20 ma high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt (a) , ana = analog ports output: od = open drain (b) , pp = push-pull a. in the interrupt input column, ?eix? defines the associ ated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then t he i/o configuration is pull- up interrupt input, else the configuration is floating interrupt input. b. in the open drain output column, ?t? defines a true open drain i/o (p -buffer and protection diode to v dd are not implemented). see section 9: i/o ports and section 12.9: i/o port pin characteristics for more details. table 2. device pin description pin no. pin name type level port main function (after reset) alternate function lqfp44 sdip42 lqfp32 sdip32 input output input output float wpu int ana od pp 6 1 30 1 pb4 (hs) i/o c t hs x ei3 x x port b4 7 2 31 2 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 8 3 32 3 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 9 4 pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 10 5 pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 11 6 pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 12 7 pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 13 8 1 4 v aref (1) s analog reference voltage for adc 14 9 2 5 v ssa (1) s analog ground voltage 15 10 3 6 pf0/mco/ain8 i/o c t xei1xxxport f0 main clock out (f cpu ) adc analog input 8 16 11 4 7 pf1 (hs)/beep i/o c t hs x ei1 x x port f1 beep signal output 17 12 pf2 (hs) i/o c t hs x ei1 x x port f2 18 13 5 8 pf4/ocmp1_a/ ain10 i/o c t xx x x xport f4 timer a output compare 1 adc analog input 10 19 14 6 9 pf6 (hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 20 15 7 10 pf7 (hs)/ extclk_a i/o c t hs x x x x port f7 timer a external clock source
pin description st72324bxx 18/193 21 v dd_0 (1) s digital main supply voltage 22 v ss_0 (1) s digital ground voltage 23 16 8 11 pc0/ocmp2_b /ain12 i/o c t xx x x xport c0 timer b output compare 2 adc analog input 12 24 17 9 12 pc1/ocmp1_b /ain13 i/o c t xx x x xport c1 timer b output compare 1 adc analog input 13 25 18 10 13 pc2 (hs)/ icap2_b i/o c t hs x x x x port c2 timer b input capture 2 26 19 11 14 pc3 (hs)/ icap1_b i/o c t hs x x x x port c3 timer b input capture 1 27 20 12 15 pc4/miso/icc data i/o c t xx x xport c4 spi master in / slave out data icc data input 28 21 13 16 pc5/mosi/ ain14 i/o c t xx x x xport c5 spi master out / slave in data adc analog input 14 29 22 14 17 pc6/sck/ iccclk i/o c t xx x xport c6 spi serial clock icc clock output 30 23 15 18 pc7/ss /ain15 i/o c t xx x x xport c7 spi slave select (active low) adc analog input 15 31 24 16 19 pa3 (hs) i/o c t hs x ei 0 xxport a3 32 25 v dd_1 (1) s digital main supply voltage 33 26 v ss_1 (1) s digital ground voltage 34 27 17 20 pa4 (hs) i/o c t hs x x x x port a4 35 28 pa5 (hs) i/o c t hs x x x x port a5 36 29 18 21 pa6 (hs) i/o c t hs x t port a6 (2) 37 30 19 22 pa7 (hs) i/o c t hs x t port a7 (2) 38 31 20 23 v pp /iccsel i must be tied low. in the flash programming mode, this pin acts as the programming voltage input v pp . see section 12.10.2 for more details. high voltage must not be applied to rom devices. 39 32 21 24 reset i/o c t top priority non maskable interrupt. 40 33 22 25 v ss_2 (1) s digital ground voltage table 2. device pin description (continued) pin no. pin name type level port main function (after reset) alternate function lqfp44 sdip42 lqfp32 sdip32 input output input output float wpu int ana od pp
st72324bxx pin description 19/193 41 34 23 26 osc2 (3) o resonator oscillator inverter output 42 35 24 27 osc1 (3) i external clock input or resonator oscillator inverter input 43 36 25 28 v dd_2 (1) s digital main supply voltage 44 37 26 29 pe0/tdo i/o c t x x x x port e0 sci transmit data out 1 38 27 30 pe1/rdi i/o c t x x x x port e1 sci receive data in 2 39 28 31 pb0 i/o c t xei2 xxport b0 caution: negative current injection not allowed on this pin (4) 3 40 pb1 i/o c t xei2 xxport b1 4 41 pb2 i/o c t xei2 xxport b2 5 42 29 32 pb3 i/o c t x ei 2 xxport b3 1. it is mandatory to connect all available v dd and v ref pins to the supply voltage and all v ss and v ssa pins to ground. 2. on the chip, each i/o port has eight pads. pads that are not b onded to external pins are in i nput pull-up configuration after reset. the configuration of these pads must be kept at reset state to avoid added current consumption. 3. osc1 and osc2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see section 1: description and section 12.6: clock and timing characteristics for more details. 4. for details refer to section 12.9.1 on page 158 table 2. device pin description (continued) pin no. pin name type level port main function (after reset) alternate function lqfp44 sdip42 lqfp32 sdip32 input output input output float wpu int ana od pp
register and memory map st72324bxx 20/193 3 register and memory map as shown in figure 6 , the mcu is capable of addressing 64 kbytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, up to 1024 bytes of ram and up to 32 kbytes of user progra m memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. caution: never access memory locations marked as ?reserved?. accessing a reserved area can have unpredictable effects on the device. figure 6. memory map 0000h ram program memory (32, 16 or 8 kbytes) interrupt and reset vectors hw registers 0080h 007fh 7fffh (see ta bl e 3 ) 8000h ffdfh ffe0h ffffh (see ta bl e 2 5 ) 0480h reserved 047fh short addressing ram (zero page) 256 bytes stack 16-bit addressing ram 0100h 01ffh 027fh 0080h 0200h 00ffh 32 kbytes 8000h ffffh or 047fh 16 kbytes c000h (1024, 512 or 384 bytes) 8 kbytes e000h table 3. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a (1) pa d r paddr pao r port a data register port a data direction register port a option register 00h (2) 00h 00h r/w r/w r/w 0003h 0004h 0005h port b (1) pbdr pbddr pbor port b data register port b data direction register port b option register 00h (2) 00h 00h r/w r/w r/w 0006h 0007h 0008h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h (2) 00h 00h r/w r/w r/w 0009h 000ah 000bh port d (1) pdadr pdddr pdor port d data register port d data direction register port d option register 00h (2) 00h 00h r/w r/w r/w 000ch 000dh 000eh port e (1) pedr peddr peor port e data register port e data direction register port e option register 00h (2) 00h 00h r/w r/w (1) r/w (1)
st72324bxx register and memory map 21/193 000fh 0010h 0011h port f (1) pfdr pfddr pfor port f data register port f data direction register port f option register 00h (2) 00h 00h r/w r/w r/w 0012h to 0020h reserved area (15 bytes) 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 0024h 0025h 0026h 0027h itc ispr0 ispr1 ispr2 ispr3 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 0028h eicr external interrupt control register 00h r/w 0029h flash fcsr flash contro l/status register 00h r/w 002ah watchdog wdgcr watchdog control register 7fh r/w 002bh si sicsr system integrity cont rol/status register 000x 000xb r/w 002ch 002dh mcc mccsr mccbcr main clock control/status register main clock controller: beep control register 00h 00h r/w r/w 002eh to 0030h reserved area (3 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tac s r ta i c 1 h r ta i c 1 l r tao c 1 h r taoc1lr tachr tac l r taachr ta ac l r ta i c 2 h r ta i c 2 l r tao c 2 h r taoc2lr timer a control register 2 timer a control register 1 timer a control/status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate co unter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxxx x0xxb xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h reserved area (1 byte) table 3. hardware register map (continued) address block register label register name reset status remarks
register and memory map st72324bxx 22/193 legend: x = undefined, r/w = read/write 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbcsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b control/status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate co unter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxxx x0xxb xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00h x000 0000b 00h 00h --- 00h read only r/w r/w r/w r/w r/w r/w 0058h to 006fh reserved area (24 bytes) 0070h 0071h 0072h adc adccsr adcdrh adcdrl control/status register data high register data low register 00h 00h 00h r/w read only read only 0073h 007fh reserved area (13 bytes) 1. the bits associated with unavailable pi ns must always keep their reset value. 2. the contents of the i/o port dr registers are readable only in output conf iguration. in input confi guration, the values of th e i/o pins are returned instead of the dr register contents. table 3. hardware register map (continued) address block register label register name reset status remarks
st72324bxx flash program memory 23/193 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features 3 flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be programmed or erased. ? icp (in-circuit programming). in this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. ? iap (in-application programming). in this mode, all sectors, except sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ict (in-circuit testing) for downloading and executing user application test patterns in ram readout protection register access security system (rass) to prevent accidental programming or erasing 4.3 structure the flash memory is organized in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see ta b l e 4 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flash memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 7 ). they are mapped in the upper part of the st7 addressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). table 4. sectors available in flash devices flash size available sectors 4 kbytes sector 0 8 kbytes sectors 0, 1 >8 kbytes sectors 0, 1, 2
flash program memory st72324bxx 24/193 4.3.1 readout protection readout protection, when selected, provides a protection against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. in flash devices, this protection is removed by reprogramming the option. in this case, the entire program memory is first automatically erased. readout protection selection depends on the device type: in flash devices it is enabled and removed through the fmp_r bit in the option byte. in rom devices it is enabled by mask option specified in the option list. figure 7. memory map and sector address 4kbytes 4kbytes sector 1 sector 0 sector 2 8k 16k 32k flash ffffh efffh dfffh 7fffh 24 kbytes memory size 8kbytes bfffh
st72324bxx flash program memory 25/193 4.4 icc interface icc needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see figure 8 ). these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input/output serial data pin ? iccsel/v pp : programming voltage ? osc1 (or oscin): main clock inpu t for external source (optional) ?v dd : application board power supply (optional, see figure 8 , note 3) figure 8. typical icc interface 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programmi ng tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not availabl e for the application. if they are used as inputs by the application, isolation such as a serial resistor has to be implemen ted in case another device forces the signal. refer to the programming tool docum entation for recommended resistor values. 2. during the icc session, the programming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset ci rcuit if it driv es more than 5ma at high level (push-pull output or pull-up resistor <1 k ). a schottky diode can be used to isolate the application reset circuit in this case. when using a classical rc network with r>1k or a reset management ic with open drain output and pull-up resistor >1 k , no additional components are needed. in all cases the user must ensure that no external reset is generated by the application dur ing the icc session. 3. the use of pin 7 of the icc connector depends on t he programming tool architecture. this pin must be connected when using most st progr amming tools (it is used to moni tor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 (oscin) pin of the st7 when the clock is not available in the application or if the select ed clock option is not programmed in t he option byte. st7 devices with multi- oscillator capability need to have osc2 grounded in this case. caution: external clock icc entry mode is mandatory in st72f324b 8/16 kbyte flash devices. in this case pin 9 must be connected to the osc1 (oscin) pin of the st7 and osc2 must be grounded. 32 kbyte flash devices may use external clock or application clock icc entry mode. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) 10 k v ss iccsel/vpp st7 osc1 osc2 mandatory for see note 1 see note 2 application reset source application i/o (see note 4) 8/16 kbyte flash devices
flash program memory st72324bxx 26/193 4.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the specific microcontroller device, the user needs only to implement the icp hardware interface on the application board (see figure 8 ). for more details on the pin locations, refer to the device pinout description. 4.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). for example, it is possible to download code from the spi, sci, usb or can interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 related documentation for details on flash programming and icc protocol, refer to the st7 flash programming reference manual and to the st7 icc protocol reference manual . 4.7.1 flash control/st atus register (fcsr) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. fcsr reset value: 0000 0000 (00h) 76543210 00000000 r/w r/w r/w r/w r/w r/w r/w r/w table 5. flash control/status register address and reset value address (hex) register label 7 6 5 4 3 2 1 0 0029h fcsr reset value 0 0 0 0 0 0 0 0
st72324bxx central processing unit (cpu) 27/193 5 central processing unit (cpu) 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 main features enable executing 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) two 8-bit index registers 16-bit stack pointer low power halt and wait modes priority maskable hardware interrupts non-maskable software/hardware interrupts 5.3 cpu registers the six cpu registers shown in figure 9 are not present in the memory mapping and are accessed by specific instructions. figure 9. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 87 0 reset value = stack higher address reset value = 1 x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
central processing unit (cpu) st72324bxx 28/193 5.3.1 accumulator (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 5.3.2 index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register.) the y register is not affected by the interrupt automatic procedures. 5.3.3 program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). 5.3.4 condition co de register (cc) the 8-bit condition code register contains the interrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. these bits can be individually tested and/or controlled by specific instructions. cc reset value: 111x1xxx 76543210 11i1hi0nzc r/w r/w r/w r/w r/w r/w r/w r/w table 6. arithmetic management bits bit name function 4h half carry this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruction. the h bit is useful in bcd arithmetic subroutines. 2n negative this bit is set and cleared by hardware. it is representative of the resu lt sign of the last arithmetic, logical or data manipulation. it is a copy of the result 7th bit. 0: the result of the last operation is positive or null. 1: the result of the last oper ation is negative (that is, the most significant bit is a logic 1. this bit is accessed by the jrmi and jrpl instructions.
st72324bxx central processing unit (cpu) 29/193 these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (isprx). they can be also set/cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see section 7: interrupts on page 41 for more details. 1z zero (arithmetic management bit) this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. 0c carry/borrow this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit te st and branch?, shift and rotate instructions. table 7. software interrupt bits bit name function 5i1 software interrupt priority 1 the combination of the i1 and i0 bits determ ines the current interrupt software priority (see ta b l e 8 ). 3i0 software interrupt priority 0 the combination of the i1 and i0 bits determ ines the current interrupt software priority (see ta b l e 8 ). table 8. interrupt software priority selection interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 01 level 2 00 level 3 (= interrupt disable) 1 1 table 6. arithmetic management bits (continued) bit name function
central processing unit (cpu) st72324bxx 30/193 5.3.5 stack pointer register (sp) the stack pointer is a 16-bit register which is always pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 10 ). since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. following an mcu reset, or af ter a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by an ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 10 . when an interrupt is received, the sp is decremented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an interrupt five locations in the stack area. figure 10. stack manipulation example sp reset value: 01 ffh 1514131211109876543210 00000001sp7sp6sp5sp4sp3sp2sp1sp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h
st72324bxx supply, reset and clock management 31/193 6 supply, reset and clock management 6.1 introduction the device includes a range of utility featur es for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. an overview is shown in figure 12 . for more details, refer to dedicated parametric section. main features optional phase locked loop (pll) for multiplying the frequency by 2 (not to be used with internal rc oscillato r in order to respect th e max. operating frequency) multi-oscillator cloc k management (mo) ? 5 crystal/ceramic resonator oscillators ? 1 internal rc oscillator reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd) ? auxiliary voltage detector (avd) with interr upt capability for mo nitoring the main supply 6.2 pll (phase locked loop) if the clock frequency input to the pll is in the range 2 to 4 mhz, the pll can be used to multiply the frequency by two to obtain an f osc2 of 4 to 8 mhz. the pll is enabled by option byte. if the pll is disabled, then f osc2 = f osc /2. caution: the pll is not recommended for applications where timing accuracy is required. furthermore, it must not be used with the internal rc oscillator. figure 11. pll block diagram 0 1 pll option bit pll x 2 f osc2 / 2 f osc
supply, reset and clock management st72324bxx 32/193 figure 12. clock, reset and supply block diagram 6.3 multi-oscillator (mo) the main clock of the st7 can be generated by three different source types coming from the multi-oscillator block: an external source 4 crystal or ceramic resonator oscillators an internal high fr equency rc oscillator each oscillator is optimized fo r a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in ta bl e 9 . refer to the electrical characteristics section for more details. caution: the osc1 and/or osc2 pins must not be left unconnected. for the purposes of failure mode and effect analysis, it should be noted that if the osc1 and/or osc2 pins are left unconnected, the st7 main oscillator may start a nd, in this configuration, could generate an f osc clock frequency in excess of the allowed maximum (> 16 mhz.), putting the st7 in an unsafe/undefined state. the product behavior must therefore be considered undefined when the osc pins are left unconnected. 6.3.1 external clock source in this external clock mode, a clock signal (s quare, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. low voltage detector (lvd) f osc2 auxiliary voltage detector (avd) multi- oscillator (mo) osc1 reset v ss v dd reset sequence manager (rsm) osc2 main clock avd interrupt request controller pll system integrity management watchdog sicsr timer (wdg) with real-time clock (mcc/rtc) avd avd lv d rf ie wdg rf f osc (option) 0 f f cpu 0 0 0
st72324bxx supply, reset and clock management 33/193 6.3.2 crystal/ceramic oscillators this family of oscillators has the advantage of prod ucing a very accurate rate on the main clock of the st7. the selection within a list of four oscillators with diff erent frequency ranges has to be done by option byte in order to reduce consumption (refer to section 14.1 on page 179 for more details on the frequency ranges). in this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as clos e as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. the loading capacitance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the rese t phase to avoid losing time in the oscillator start-up phase. 6.3.3 internal rc oscillator this oscillator allows a low cost solution for the main clock of the st7 using only an internal resistor and capacitor. internal rc oscillato r mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. in this mode, the two oscillator pins have to be tied to ground. in order not to exceed the maximum operating frequency, the in ternal rc oscillator must not be used with the pll. table 9. st7 clock sources hardware configuration external clock crystal/ceramic resonators internal rc oscillator osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7
supply, reset and clock management st72324bxx 34/193 6.4 reset sequence manager (rsm) the reset sequence manager includes three reset sources as shown in figure 14 : external reset source pulse internal lvd reset internal watchdog reset these sources act on the reset pin and it is always kept low during the delay phase. the reset service routine vector is fixed at addresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of three phases as shown in figure 13 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (selected by option byte) reset vector fetch caution: when the st7 is unprogrammed or fully erased, the flash is blank and the reset vector is not programmed. for this reason, it is recommended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. the reset vector fetch phase duration is two clock cycles. figure 13. reset sequence phases 6.4.1 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. see the electrical characteristics section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 15 ). this detection is asynchronous and therefore the mcu can enter reset state even in halt mode. reset active phase internal reset 256 or 4096 clock cycles fetch vector
st72324bxx supply, reset and clock management 35/193 figure 14. reset block diagram the reset pin is an asynchronous sign al which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specif ied for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc network connected to the reset pin. internal lvd reset two different reset sequences caused by the internal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd supply, reset and clock management st72324bxx 36/193 figure 15. reset sequences 6.5 system integrity management (si) the system integrity management block cont ains the lvd and auxiliary voltage detector (avd) functions. it is managed by the sicsr register. 6.5.1 lvd (low voltage detector) the lvd function generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power- on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: ?v it+ when v dd is rising ?v it- when v dd is falling the lvd function is illustrated in figure 15 . the voltage threshold can be configured by option byte to be low, medium or high. v dd run reset pin external watchdog active phase v it+(lvd) v it-(lvd) t h(rstl)in run watchdog underflow t w(rstl)out run run reset reset source external reset lvd reset watchdog reset internal reset (256 or 4096 t cpu ) vector fetch active phase active phase
st72324bxx supply, reset and clock management 37/193 provided the minimum v dd value (guaranteed for the osc illator frequency) is above v it- , the mcu can only be in two modes: ? under full software control ? in static safe reset in these conditions, secure operation is always ensured for the application without the need for external reset hardware. during an lvd reset, the reset pin is held low, thus permitting the mcu to reset other devices. note: 1 the lvd allows the device to be used without any external reset circuitry. 2 if the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. below 3.8 v, device operation is not guaranteed. 3 the lvd is an optional function which can be selected by option byte. 4 it is recommended to make sure that the v dd supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly. figure 16. low voltage detector vs reset 6.5.2 avd (auxiliary voltage detector) the avd is based on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main supply. the v it- reference value for falling voltage is lower than the v it+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). the output of the avd comparator is directly readable by the application software through a real-time status bit (avdf) in the sicsr register. this bit is read only. caution: the avd function is active only if the lv d is enabled through the option byte (see section 14.1 on page 179 ). monitoring the v dd main supply the avd voltage threshold value is relative to the selected lvd threshold configured by option byte (see section 14.1 on page 179 ). if the avd interrupt is enabled, an interrupt is generated when the voltage crosses the v it+(avd) or v it-(avd) threshold (avdf bit toggles). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcontroller. see figure 17 . v dd v it+ reset v it- v hys
supply, reset and clock management st72324bxx 38/193 the interrupt on the rising edge is used to inform the application that the v dd warning state is over. if the voltage rise time t rv is less than 256 or 4096 cpu cycles (depending on the reset delay selected by option byte), no avd interrupt will be generated when v it+(avd) is reached. if t rv is greater than 256 or 4096 cycles then: if the avd interrupt is enabled before the v it+(avd) threshold is reached, then 2 avd interrupts will be received: the first when the avdie bit is set, and the second when the threshold is reached. if the avd interrupt is enabled after the v it+(avd) threshold is reached then only one avd interrupt will occur. figure 17. using the avd to monitor v dd 6.5.3 low power modes 6.5.4 interrupts the avd interrupt event generates an interrupt if the avdie bit is set and the interrupt mask in the cc register is re set (rim instruction). m v dd v it+(avd) v it-(avd) avdf bit 0 0 reset value if avdie bit = 1 v hyst avd interrupt request interrupt process interrupt process v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 1 1 t rv voltage rise time table 10. effect of low power modes on si mode description wait no effect on si. avd interrupt causes the device to exit from wait mode. halt the crsr register is frozen. table 11. avd interrupt control/wakeup capability interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no
st72324bxx supply, reset and clock management 39/193 6.6 si registers 6.6.1 system integrity (si) con trol/status register (sicsr) sicsr reset value: 000x 000x (00h) 76543210 res avdie avdf lvdrf reserved wdgrf - r/w ro r/w - r/w table 12. sicsr register description bit name function 7 - reserved, must be kept cleared 6avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag changes (toggles). the pending interrupt information is automatically cleared when software enters the avd interrupt routine 0: avd interrupt disabled 1: avd interrupt enabled 5avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is generated when the avdf bit changes value. refer to figure 17 and to section 6.5.2: avd (auxiliary voltage detector) for additional details. 0: v dd over v it+(avd) threshold 1: v dd under v it-(avd) threshold 4 lvdrf lvd reset flag this bit indicates that the last reset was generated by the lvd block. it is set by hardware (lvd reset) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. 3:1 - reserved, must be kept cleared 0 wdgrf watchdog reset flag this bit indicates that the last reset was generated by the watchdog peripheral. it is set by hardware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf information, the flag description is given in table 13 . table 13. reset source flags reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lv d 1 x
supply, reset and clock management st72324bxx 40/193 application notes the lvdrf flag is not cleared when another re set type occurs (external or watchdog); the lvdrf flag remains set to keep trace of the original failure. in this case, a watchdog reset can be detected by software while an external reset cannot. caution: when the lvd is not activated with the associated option byte, the wdgrf flag can not be used in the application.
st72324bxx interrupts 41/193 7 interrupts 7.1 introduction the st7 enhanced interrupt management provides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrupt priority and level management: ? up to 4 software programmable nesting levels ? up to 16 interrupt vectors fixed by hardware ? 2 non-maskable events: reset, trap this interrupt management is based on: bit 5 and bit 3 of the cpu cc register (i1:0) interrupt software priority registers (isprx) fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order this enhanced in terrupt controller guarant ees full upward compatib ility with the standard (not nested) st7 interrupt controller. 7.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see ta bl e 1 4 ). the processing flow is shown in figure 18. when an interrupt request has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to table 25: interrupt mapping for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, th e i1 and i0 bits will be restored from the stack and the program in the pr evious level will resume.
interrupts st72324bxx 42/193 figure 18. interrupt processing flowchart 7.2.1 servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. figure 19 describes this decision process. figure 19. priority decision process flowchart table 14. interrupt software priority levels interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 ?iret? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset trap pending i nstruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction i nterrupt pending software different interrupts same highest hardware priority serviced priority highest software priority serviced
st72324bxx interrupts 43/193 when an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. note: 1 the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. 2 reset and trap can be considered as having the highest software priority in the decision process. 7.2.2 different inte rrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, trap) and the maskable type (external or from internal peripherals). 7.2.3 non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 18 ). after stacking the pc, x, a and cc registers (except for reset), the corresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. trap (non-maskable software interrupt) this software interrupt is serv iced when the trap instruction is executed. it will be serviced according to the flowchart in figure 18 . reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the highest hardware priority. see the reset chapter for more details. 7.2.4 maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if an y of these two conditions is false, the interrupt is latched and thus remains pending. external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the external interrupt control register (eicr). external interrupt triggered on edge will be la tched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in table 25: interrupt mapping . a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the
interrupts st72324bxx 44/193 peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note: the clearing sequence resets the internal latch. a pending interrupt (that is, waiting to be serviced) is therefore lost if the clear sequence is executed. 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column exit from halt in table 25: interrupt mapping ). when several pending interrupts are present while exiting halt mode, the first one se rviced can only be an interrupt with exit from halt mode capability and it is selected th rough the same decision process shown in figure 19 . note: if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 7.4 concurrent and nested management figure 20 and figure 21 show two different interrupt management modes. the first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in figure 21 . the interrupt hardware priority is given in order from the lowest to the highest as follows: main, it4, it3, it2, it1, it0. software priority is given for each interrupt. warning: a stack overflow may occur without notifying the software of the failure. figure 20. concurrent interrupt management main it4 it2 it1 trap it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11/10 11 rim it2 it1 it4 trap it3 it0 it3 i0 10 priority level used stack = 10 bytes
st72324bxx interrupts 45/193 figure 21. nested interrupt management 7.5 interrupt registers 7.5.1 cpu cc regist er interrupt bits these two bits indicate the current interrupt software priority (see ta b l e 1 6 ) and are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop instructions (see table 18: dedicated interrupt instruction set ). main it2 trap main it0 it2 it1 it4 trap it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes cpu cc reset value: 111x 1010(xah) 76543210 11 i1 h i0 nzc r/w r/w r/w r/w r/w r/w r/w r/w table 15. cpu cc register interrupt bits description bit name function 5 i1 software interrupt priority 1 3 i0 software interrupt priority 0 table 16. interrupt software priority levels interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) (1) 1. trap and reset events can interrupt a level 3 program. 11
interrupts st72324bxx 46/193 7.5.2 interrupt software pr iority registers (isprx) these four registers contain the interrupt software priority of each interrupt vector. each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this correspondence is shown in the following ta b l e 1 7 . each i1_x and i0_x bit value in the isprx registers has the same meaning as the i1 and i0 bits in the cc register. level 0 cannot be written (i1_x = 1, i0_x = 0). in this case, the previously stored value is kept (for example, previous value = cfh, write = 64h, result = 44h). the reset, and trap vectors have no software priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. caution: if the i1_x and i0_x bits are modified while the interrupt x is executed the following behavior has to be considered: if the inte rrupt x is still pending (new inte rrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the interrupt x). isprx reset value: 1111 1111 (ffh) 76543210 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 r/wr/wr/wr/wr/wr/wr/wr/w ispr31111i1_13i0_13i1_12i 0_12 ro ro ro ro r/w r/w r/w r/w table 17. isprx interrupt vector correspondence vector address isprx bits fffbh-fffah i1_0 and i0_0 bits fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits table 18. dedicated interrupt instruction set (1) instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0=11 (level 3) i1:0=11 ? jrnm jump if i1:0<>11 i1:0<>11 ?
st72324bxx interrupts 47/193 pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 1. during the execution of an interrupt routine, t he halt, pop cc, rim, sim and wfi instructions change the current software priority up to the next iret instru ction or one of the previously mentioned instructions. table 18. dedicated interrupt instruction set (1) (continued) instruction new description function/example i1 h i0 n z c
interrupts st72324bxx 48/193 7.6 external interrupts 7.6.1 i/o port in terrupt sensitivity the external interrupt sensitivity is controlled by the ipa, ipb and isxx bits of the eicr register ( figure 22 ). this control allows up to four fully independent external interrupt source sensitivities. each external interrupt source can be generated on four (or five) different events on the pin: falling edge rising edge falling and rising edge falling edge and low level rising edge and high level (only for ei0 and ei2) to guarantee correct functionality, the sensitivity bits in the eicr register can be modified only when the i1 and i0 bits of the cc register are both set to 1 (level 3). this means that interrupts must be disabled before changing sensitivity. the pending interrupts are cleared by writing a different value in the isx[1:0], ipa or ipb bits of the eicr. figure 22. external interrupt control bits is10 is11 eicr pbor.3 pbddr.3 ipb bit pb3 ei2 interrupt source port b [3:0] interrupts pb3 pb2 pb1 pb0 is10 is11 eicr pbor.4 pbddr.4 pb4 ei3 interrupt source port b4 interrupt is20 is21 eicr paor.3 paddr.3 ipa bit pa3 ei0 interrupt source port a3 interrupt is20 is21 eicr pfor.2 pfddr.2 pf2 ei1 interrupt source port f [2:0] interrupts pf2 pf1 pf0 sensitivity control sensitivity control sensitivity sensitivity control control
st72324bxx interrupts 49/193 7.6.2 external interrupt control register (eicr) eicr reset value: 0000 0000 (00h) 76543210 is11 is10 ipb is21 is20 ipa reserved r/w r/w r/w r/w r/w r/w - table 19. eicr register description bit name function 7:6 is1[1:0] ei2 and ei3 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the following external interrupts: - ei2 for port b [3:0] (see ta bl e 2 0 ) - ei3 for port b4 (see ta b l e 2 1 ) bits 7 and 6 can only be written when i1 an d i0 of the cc register are both set to 1 (level 3). 5ipb interrupt polarity (for port b) this bit is used to invert the sensitivity of port b [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion 4:3 is2[1:0] ei0 and ei1 sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts: - ei0 for port a[3:0] (see ta b l e 2 2 ) - ei1 for port f[2:0] (see ta bl e 2 3 ) bits 4 and 3 can only be written when i1 an d i0 of the cc register are both set to 1 (level 3). 2ipa interrupt polarity (for port a) this bit is used to invert the sensitivity of port a [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion. 1: sensitivity inversion. 1:0 - reserved, must always be kept cleared table 20. interrupt sensitivity - ei2 is11 is10 external interrupt sensitivity ipb bit = 0 ipb bit = 1 0 0 falling edge and low level rising edge and high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge
interrupts st72324bxx 50/193 table 21. interrupt sensitivity - ei3 is11 is10 external interrupt sensitivity 0 0 falling edge and low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge table 22. interrupt sensitivity - ei0 is21 is20 external interrupt sensitivity ipa bit = 0 ipa bit = 1 0 0 falling edge and low level rising edge and high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge table 23. interrupt sensitivity - ei1 is21 is20 external interrupt sensitivity 0 0 falling edge and low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge table 24. nested interrupts register map and reset values address (hex.)register label76543210 0024h ispr0 reset value ei1 ei0 mcc + si i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 0025h ispr1 reset value spi ei3 ei2 i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0026h ispr2 reset value avd sci timer b timer a i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0027h ispr3 reset value 1111 i1_13 1 i0_13 1 i1_12 1 i0_12 1 0028h eicr reset value is11 0 is10 0 ipb 0 is21 0 is20 0 ipa 000
st72324bxx interrupts 51/193 table 25. interrupt mapping no. source block description register label priority order exit from halt/active-halt address vector reset reset n/a yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 not used fffah-fffbh 1 mcc/rtc main clock controller time base interrupt mccsr higher priority yes fff8h-fff9h 2 ei0 external interrupt port a3..0 n/a yes fff6h-fff7h 3 ei1 external interrupt port f2..0 yes fff4h-fff5h 4 ei2 external interrupt port b3..0 yes fff2h-fff3h 5 ei3 external interrupt port b7..4 yes fff0h-fff1h 6 not used ffeeh-ffefh 7 spi spi peripheral interrupts spicsr yes ffech-ffedh 8 timer a timer a peripheral interrupts tasr no ffeah-ffebh 9 timer b timer b peripheral interrupts tbsr no ffe8h-ffe9h 10 sci sci peripheral interrupts scisr lower priority no ffe6h-ffe7h 11 avd auxiliary voltage detector interrupt sicsr no ffe4h-ffe5h
power saving modes st72324bxx 52/193 8 power saving modes 8.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 23 ): slow, wait (slow wait), active-halt and halt. after a reset the normal operating mode is selected by default (run mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main osc illator frequency divided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. figure 23. power saving mode transitions 8.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the mccsr register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the master clock frequency (f osc2 ) can be divided by 2, 4, 8 or 16. the cpu and peripherals are clocked at this lower frequency (f cpu ). note: slow-wait mode is activated when entering the wait mode while the device is already in slow mode. power consumption wait slow run active halt high low slow wait halt
st72324bxx power saving modes 53/193 figure 24. slow mode clock transitions 8.3 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i[1:0] bits of the cc register are forced to ?10?, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the inte rrupt or reset servic e routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 25 . figure 25. wait mode flowchart 1. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. 00 01 sms cp1:0 f cpu new slow normal run mode mccsr frequency request request f osc2 f osc2 /2 f osc2 /4 f osc2 wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 10 on cpu oscillator peripherals i[1:0] bits on on xx (1) on 256 or 4096 cpu clock cycle delay
power saving modes st72324bxx 54/193 8.4 active-halt and halt modes active-halt and halt modes are the two lowest power consumption modes of the mcu. they are both entered by executing the ?halt? instruction. the decision to enter either in active- halt or halt mode is given by the mcc/rtc interrupt enable flag (oie bit in the mccsr register). 8.4.1 active-halt mode active-halt mode is the lowest power consumption mode of the mcu with a real-time clock available. it is entered by executing the ?halt? instruction when the oie bit of the main clock controller status register (mccsr) is set (see section 10.2: main clock controller with real- time clock and beeper (mcc/rtc) on page 69 for more details on the mccsr register). the mcu can exit active-halt mode on reception of either an mcc/rtc interrupt, a specific interrupt (see table 25: interrupt mapping ) or a reset. when exiting active-halt mode by means of an interrupt, no 256 or 4096 cpu cycle delay occurs. the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 27 ). when entering active-halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable interrupts. therefore, if an interrup t is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillator and its associ ated counter (mcc/rtc) are running to keep a wakeup time base. all other peripherals are not clocked except those which get their clock supply from another cloc k generator (such as external or auxiliary oscillator). the safeguard against staying locked in active-halt mode is provided by the oscillator interrupt. note: as soon as the interrupt capab ility of one of the oscillators is selected (mccsr.oie bit set), entering active-halt mode while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. caution: when exiting active-halt mode following an interr upt, oie bit of mccsr register must not be cleared before t delay after the interrupt occurs (t delay = 256 or 4096 t cpu delay depending on option byte). otherwise, the st7 enters halt mode for the remaining t delay period. figure 26. active-halt timing overview 1. this delay occurs only if the mcu exit s active-halt mode by means of a reset. table 26. mcc/rtc low power mode selection mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active-halt mode halt run run 256 or 4096 cpu cycle delay (1) reset or interrupt halt instruction fetch vector active [mccsr.oie = 1]
st72324bxx power saving modes 55/193 figure 27. active-halt mode flowchart 1. peripheral clocked with an external clock source can still be active. 2. only the mcc/rtc interrupt and some specific interr upts can exit the mcu from active-halt mode (such as external interrupt). refer to table 25: interrupt mapping on page 51 for more details. 3. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and restored when the cc register is popped. 8.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the ?halt? instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 10.2: main clock controller with real-time clock and beeper (mcc/rtc) on page 69 for more details on the mccsr register). the mcu can exit halt mode on reception of either a specific interrupt (see ta bl e 2 5 : interrupt mapping ) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and t he 256 or 4096 cpu cycl e delay is used to stabilize the oscillator. after th e start up delay, the cpu resu mes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 29 ). when entering halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillator is turned off causing all internal proc essing to be stopped, including the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of watc hdog operation with halt mode is configured by the ?wdghalt? option bit of the option byte. the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset (see section 14.1 on page 179 ) for more details. halt instruction reset interrupt (2) y n n y cpu oscillator peripherals (1) i[1:0] bits on off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx (3) on cpu oscillator peripherals i[1:0] bits on on xx (3) on 256 or 4096 cpu clock cycle delay (mccsr.oie = 1)
power saving modes st72324bxx 56/193 figure 28. halt timing overview figure 29. halt mode flowchart 1. wdghalt is an option bit. see section 14.1 on page 179 for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 25: interrupt mapping for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie = 0] halt instruction reset interrupt (3) y n n y cpu oscillator peripherals (2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx (4) on cpu oscillator peripherals i[1:0] bits on on xx (4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt (1) 0 watchdog reset 1 (mccsr.oie = 0) cycle
st72324bxx power saving modes 57/193 halt mode recommendations make sure that an external event is available to wake up the microcontroller from halt mode. when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitializ e the sensitivity level of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0x8e . to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the interrupt ma sk in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt).
i/o ports st72324bxx 58/193 9 i/o ports 9.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs, and for specific pins: external interrupt generation, alternate signal input/output for the on-chip peripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 functional description each port has two main registers: data register (dr) data direction register (ddr) and one optional register: option register (or) each i/o pin may be programmed using the corresponding register bits in the ddr and or registers: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not provide this register refer to section 9.3: i/o port implementation on page 62 ). the generic i/o block diagram is shown in figure 30. 9.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. note: 1 writing the dr register modifies the latch value but does not affect the pin status. 2 when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3 do not use read/modify/write instructions (bset or bres) to modify the dr register as this might corrupt the dr content for i/os configured as input.
st72324bxx i/o ports 59/193 external interrupt function when an i/o is configured as ?input with interrupt?, an event on this i/o can generate an external interrupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the eicr register. each external interrupt vector is linked to a dedicated group of i/o port pins (see pinout description and interrupt section). if several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the eicr register and then logically ored. the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the eicr register must be modified. 9.2.2 output modes the output conf iguration is selected by setting the co rresponding ddr regist er bit. in this case, writing the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. 9.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digi tally readable by addressing the dr register. note: input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. table 27. dr register value and output pin status dr push-pull open-drain 0v ss v ss 1v dd floating
i/o ports st72324bxx 60/193 figure 30. i/o port general block diagram table 28. i/o port mode options configuration mode pull-up p-buffer diodes to v dd (1) 1. the diode to v dd is not implemented in the true open drain pads. to v ss (2) 2. a local protection between the pad and v ss is implemented to protect the device against positive stress. input floating with/without interrupt off (3) 3. off = implemented not activated. off on on pull-up with/without interrupt on (4) 4. on = implemented and activated. output push-pull off on open drain (logic level) off true open drain ni ni ni (5) 5. ni = not implemented dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table 24 below) n-buffer pull-up (see table 24 below) 1 0 analog input if implemented v dd diodes (see table 24 below) cmos register access external interrupt source (ei x ) alternate input schmitt trigger
st72324bxx i/o ports 61/193 caution: the alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. table 29. i/o port configurations hardware configuration input (1) 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate function output status. open-drain output (2) 2. when the i/o port is in output configuration and t he associated alternate func tion is enabled as an input, the alternate function reads the pin stat us given by the dr register content. push-pull output (2) v dd r pu w r true open drain not implemented in i/o ports pad pull-up condition dr register dr register access data bus alternate input external interrupt source (ei x ) interrupt condition analog input pad r pu r/w v dd dr register access dr register true open drain not implemented in i/o ports data bus alternate output alternate enable pad r pu dr r/w v dd true open drain not implemented in i/o ports dr register access register data bus alternate enable alternate output
i/o ports st72324bxx 62/193 analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected analog pin. warning: the analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific feature of the i/o port such as adc input or true open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommend ed safe transitions are illustrated in figure 31. other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 31. interrupt i/o port state transitions 9.4 low power modes 9.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or table 30. effect of low power modes on i/o ports mode description wait no effect on i/o ports. external interrupt s cause the device to exit from wait mode. halt no effect on i/o ports. external interrupt s cause the device to exit from halt mode.
st72324bxx i/o ports 63/193 9.5.1 i/o port implementation the i/o port register configurations are summarized ta bl e 3 2 . table 31. i/o port interrupt control/wakeup capability interrupt event event flag enable contro l bit exit from wait exit from halt external interrupt on selected external event - ddrx, orx yes yes table 32. port configuration port pin name input (ddr = 0) output (ddr = 1) or = 0 or = 1 or = 0 or = 1 port a pa7:6 floating true open-drain (high sink) pa5:4 floating pull-up open drain push-pull pa3 floating floating interrupt open drain push-pull port b pb3 floating floating interrupt open drain push-pull pb4, pb2:0 floating pull-up open drain push-pull port c pc7:0 floating pull-up open drain push-pull port d pd5:0 floating pull-up open drain push-pull port e pe1:0 floating pull-up open drain push-pull port f pf7:6, 4 floating pull- up open drain push-pull pf2:0 floating pull-up open drain push-pull table 33. i/o port register map and reset values address (hex.) register label 7 6 5 43210 reset value of all i/o port registers00000000 0000h padr msb lsb 0001h paddr 0002h paor 0003h pbdr msb lsb 0004h pbddr 0005h pbor 0006h pcdr msb lsb 0007h pcddr 0008h pcor 0009h pddr msb lsb 000ah pdddr 000bh pdor
i/o ports st72324bxx 64/193 000ch pedr msb lsb 000dh peddr 000eh peor 000fh pfdr msb lsb 0010h pfddr 0011h pfor table 33. i/o port register map and reset values address (hex.) register label 7 6 5 43210
st72324bxx on-chip peripherals 65/193 10 on-chip peripherals 10.1 watchdog timer (wdg) 10.1.1 introduction the watchdog timer is used to detect the oc currence of a software fault, usually generated by external interference or by unforeseen lo gical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time period, unless the program refreshes the counter?s contents before the t6 bit becomes cleared. 10.1.2 main features programmable free-running downcounter programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 10.1.3 functional description the counter value stored in the watchdog control register (wdgcr bits t[6:0]), is decremented every 16384 f osc2 cycles (approx.), and the lengt h of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 become s cleared), it initiates a rese t cycle pulling low the reset pin for typically 30s. the application program must write in the wd gcr register at regular intervals during normal operation to prevent an mcu reset. this downcounter is free-running: it counts down even if the watchdog is disabled. the value to be stored in the wdgcr register must be between ffh and c0h: the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an immediate reset the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see figure 33: approximate timeout duration ). the timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the wdgcr register (see figure 34 ). following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction generates a reset.
on-chip peripherals st72324bxx 66/193 figure 32. watchdog block diagram 10.1.4 how to program the watchdog timeout figure 33 shows the linear relationship between the 6-bit value to be loaded in the watchdog counter (cnt) and th e resulting timeout duration in milliseconds. this can be used for a quick calculation without taking the timing variations into account. if more precision is needed, use the formulae in figure 34 . caution: when writing to the wdgcr register, always write 1 in the t6 bit to avoid generating an immediate reset. figure 33. approximate timeout duration reset wdga 6-bit downcounter (cnt) f osc2 t6 t0 wdg prescaler watchdog control register (wdgcr) div 4 t1 t2 t3 t4 t5 12-bit mcc rtc counter lsb div 64 0 5 6 11 mcc/rtc tb[1:0] bits (mccsr register) msb cnt value (hex.) watchdog timeout (ms) @ 8 mhz. f osc2 3f 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114
st72324bxx on-chip peripherals 67/193 figure 34. exact timeout duration (t min and t max ) where : t min0 = (lsb + 128) x 64 x t osc2 t max0 = 16384 x t osc2 t osc2 = 125 ns if f osc2 =8 mhz cnt = value of t[5:0] bits in the wdgcr register (6 bits) msb and lsb are values from the table below depending on the timebase selected by the tb[1:0] bits in the mccsr register to calculate the minimum watchdog timeout (t min ): if then else to calculate the maximum watchdog timeout (t max ): if then else note: in the above formulae, division results must be rounded down to the next integer value. example : with 2ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mccsr reg.) selected mccsr timebase msb lsb 00 2 ms459 01 4 ms853 1 0 10 ms 20 35 1 1 25 ms 49 54 value of t[5:0] bits in wdgcr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t max 00 1.496 2.048 3f 128 128.552 cnt msb 4 ------------- < t min t min0 16384 cnt t osc2 + = t min t min0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = cnt msb 4 ------------- t max t max0 16384 cnt t osc2 + = t max t max0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + =
on-chip peripherals st72324bxx 68/193 10.1.5 low power modes 10.1.6 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the wdgcr is not used. refer to the option byte description in section 14.1: flash devices . 10.1.7 using halt mode with the wdg (wdghalt option) the following recommendation applies if halt mode is used when the watchdog is enabled: before executing the halt instruction, refresh the wdg counter to avoid an unexpected wdg reset immediately after waking up the microcontroller. 10.1.8 interrupts none. table 34. effect of lower power modes on watchdog mode description slow no effect on watchdog wait halt oie bit in mccsr register wdghalt bit in option byte 00 no watchdog reset is generated. the mcu enters halt mode. the watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the mcu receives an external interrupt or a reset. if an external interrupt is received, the watchdog restarts counting after 256 or 4096 cpu clocks. if a reset is generated, the watchdog is disabled (reset state) unless hardware wa tchdog is selected by option byte. for application recommendations, see section 10.1.7 below. 0 1 a reset is generated. 1x no reset is generated. the mcu enters active-halt mode. the watchdog counter is not decremented. it stop counting. when the mcu receives an oscillator interrupt or external interrupt, the watchdog restarts counting immediately. when the mcu receives a reset the watchdog restarts counting after 256 or 4096 cpu clocks.
st72324bxx on-chip peripherals 69/193 10.1.9 control register (wdgcr) 10.2 main clock controller with real-time clock and beeper (mcc/rtc) the main clock controller consists of three different functions: a programmable cpu clock prescaler a clock-out signal to supply external devices a real-time clock timer with interrupt capability each function can be used independently and simultaneously. 10.2.1 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal peripherals. it manages slow power saving mode (see section 8.2: slow mode on page 52 for more details). the prescaler selects the f cpu main clock frequency and is controlled by three bits in the mccsr register: cp[1:0] and sms. wdgcr reset value: 0111 1111 (7fh) 76543210 wdga t[6:0] r/w r/w table 35. wdgcr register description bit name function 7wdga activation bit this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watchdog option is enabled by option byte. 6:0 t[6:0] 7-bit counter (msb to lsb) these bits contain the value of the watchdog counter, which is decremented every 16384 f osc2 cycles (approx.). a reset is produced when it rolls over from 40h to 3fh (t6 is cleared). table 36. watchdog timer register map and reset values address (hex.)register label76543210 002ah wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
on-chip peripherals st72324bxx 70/193 10.2.2 clock-out capability the clock-out capability is an alternate function of an i/ o port pin that outputs the f cpu clock to drive external devices. it is controlled by the mco bit in the mccsr register. caution: when selected, the clock out pin suspends the clock during active-halt mode. 10.2.3 real-time clock (rtc) timer the counter of the real-time clock timer allows an interrupt to be generated based on an accurate real-time clock. four different time bases depending directly on f osc2 are available. the whole functionality is controlled by four bits of the mccsr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active-halt mode when the halt instruction is executed. see section 8.4: active-halt and halt modes on page 54 for more details. 10.2.4 beeper the beep function is controlled by the mccbcr register. it can output three selectable frequencies on the beep pin (i/o port alternate function). figure 35. main clock controller (mcc/rtc) block diagram div 2, 4, 8, 16 mcc/rtc interrupt sms cp1 cp0 tb1 tb0 oie oif cpu clock mccsr 12-bit mcc rtc counter to cpu and peripherals f osc2 f cpu mco mco bc1 bc0 mccbcr beep selection beep signal 1 0 to watchdog timer div 64
st72324bxx on-chip peripherals 71/193 10.2.5 low power modes 10.2.6 interrupts the mcc/rtc interrupt event generates an interrupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). 10.2.7 mcc registers mcc control/status register (mccsr) ) table 37. effect of low power modes on mcc/rtc mode description wait no effect on mcc/rtc peripheral. mcc/rtc interrupt causes the device to exit from wait mode. active-halt no effect on mcc/rtc counter (oie bi t is set), the registers are frozen. mcc/rtc interrupt causes the device to exit from active-halt mode. halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with exit from halt capability. table 38. mcc/rtc interrupt control/wakeup capability interrupt event event flag en able control bit exit from wait exit from halt time base overflow event oif oie yes no (1) 1. the mcc/rtc interrupt wakes up the mcu from active-halt mode, not from halt mode. mccsr reset value: 0000 0000 (00h) 76543210 mco cp[1:0] sms tb[1:0] oie oif r/w r/w r/w r/w r/w r/w table 39. mccsr register description bit name function 7mco main clock out selection this bit enables the mco alternate function on the pf0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o). 1: mco alternate function enabled (f cpu on i/o port). note: to reduce power consumption, the mc o function is not ac tive in active-halt mode.
on-chip peripherals st72324bxx 72/193 . 6:5 cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software: 00: f cpu in slow mode = f osc2 /2 01: f cpu in slow mode = f osc2 /4 10: f cpu in slow mode = f osc2 /8 11: f cpu in slow mode = f osc2 /16 4sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu =f osc2 . 1: slow mode. f cpu is given by cp1, cp0. see section 8.2: slow mode and section 10.2: main clock controller with real-time clock and beeper (mcc/rtc) for more details. 3:2 tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software (see ta bl e 4 0 ). a modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. this allows to use this time base as a real-time clock. 1oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active-halt mode. when this bit is set, calling the st7 software halt instruction enters the active-halt power saving mode . 0oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the mccsr register. it indicates when set that the main oscillat or has reached the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution : the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. table 40. time base selection counter prescaler time base tb1 tb0 f osc2 =4mhz f osc2 =8mhz 16000 4 ms 2 ms 0 0 32000 8 ms 4 ms 0 1 80000 20 ms 10 ms 1 0 200000 50 ms 25 ms 1 1 table 39. mccsr register description (continued) bit name function
st72324bxx on-chip peripherals 73/193 mcc beep control register (mccbcr) mccbcr reset value: 0000 0000 (00h) 76543210 reserved bc[1:0] -r/w table 41. mccbcr register description bit name function 7:2 - reserved, must be kept cleared 1:0 bc[1:0] beep control these 2 bits select the pf1 pin beep capability (see ta b l e 4 2 ). the beep output signal is available in active-halt mode but has to be disabled to reduce the consumption. table 42. beep frequency selection bc1 bc0 beep mode with f osc2 =8mhz 00 off 0 1 ~2 khz output beep signal ~50% duty cycle 1 0 ~1 khz 11 ~500hz table 43. main clock controller register map and reset values address (hex.) register label7654321 0 002bh sicsr reset value 0 avdie 0 avdf 0 lvdrf x000 wdgrf x 002ch mccsr reset value mco 0 cp1 0 cp0 0 sms 0 tb1 0 tb0 0 oie 0 oif 0 002dh mccbcr reset value000000 bc1 0 bc0 0
on-chip peripherals st72324bxx 74/193 10.3 16-bit timer 10.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and pwm). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequencies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 10.3.2 main features programmable prescaler: f cpu divided by 2, 4 or 8 overflow status flag and maskable interrupt external clock input (must be at least four times slower than the cpu clock speed) with the choice of active edge 1 or 2 output compare functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt 1 or 2 input capture functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk) (c) the timer block diagram is shown in figure 36 . c. some timer pins may not be available (not bonded) in so me st7 devices. refer to section 2: pin description . when reading an input signal on a non-bonded pin, the value will always be ?1?.
st72324bxx on-chip peripherals 75/193 10.3.3 functional description counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high and low. counter register (cr) ? counter high register (chr) is the most significant byte (msb) ? counter low register (clr) is the least significant byte (lsb) alternate counter register (acr) ? alternate counter high register (achr) is the most significant byte (msb) ? alternate counter low register (aclr) is the least significant byte (lsb) these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register (sr) (see note at the end of paragraph entitled 16-bit read sequence) . writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit timer). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bi ts of the cr2 register, as illustrated in ta bl e 5 0 . the value in the counter register repeats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency.
on-chip peripherals st72324bxx 76/193 figure 36. timer block diagram 1. if ic, oc and to interrupt requests have separat e vectors then the last or is not present (see table 25: interrupt mapping on page 51 ). mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch 1 ocmp1 icap1 extclk fcpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch 2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) csr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit 1 edge detect circuit 2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] pin pin pin pin pin register (see note 1) counter register
st72324bxx on-chip peripherals 77/193 16-bit read sequence the 16-bit read sequence (from either the counter register or the alternate counter register) is illustrated in the following figure 37 . figure 37. 16-bit read sequence the user must first read the msb, afterwhi ch the lsb value is automatically buffered. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. after a complete reading sequence, if only the clr register or aclr register are read, they return the lsb of the count value at the time of the read. whatever the timer mode used (input capture, output compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interr upt remains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by access to th e aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). read at t0 read returns the buffered lsb value at t0 at t0 + t other instructions beginning of the sequence sequence completed lsb is buffered lsb msb
on-chip peripherals st72324bxx 78/193 external clock the external clock (where available) is selected if cc0 = 1 and cc1 = 1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the external clock pin extclk that will trigger the free running counter. the counter is synchronize d with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur betw een two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the cpu clock frequency. figure 38. counter timing diagram, internal clock divided by 2 figure 39. counter timing diagram, internal clock divided by 4 figure 40. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
st72324bxx on-chip peripherals 79/193 input capture in this section, the index, i , may be 1 or 2 because there are two input capture functions in the 16-bit timer. the two 16-bit input capture registers (ic1r/ic2r) are used to latch the value of the free running counter after a transition is detected on the icap i pin (see figure 42 ). the icir registers are read-only registers. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure to use the input capture function select the following in the cr2 register: select the timer clock (cc[1:0]) (see ta bl e 5 0 ). select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). when an input capture occurs: icf i bit is set. the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 42 ). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set 2. an access (read or write) to the ic i lr register table 44. input capture byte distribution register ms byte ls byte icir ic i hr ic i lr
on-chip peripherals st72324bxx 80/193 note: 1 after reading the icihr regist er, transfer of input capture data is inhibited and icfi will never be set until the icilr re gister is also read. 2 the icir register contains the free running counter value which corresponds to the most recent input capture. 3 the two input capture functions can be used together even if the timer also uses the two output compare functions. 4 in one pulse mode and pwm mode only input capture 2 can be used. 5 the alternate inputs (icap1 and icap2) are always directly connected to the timer. so any transitions on these pins activates the input capture function. moreover if one of the icapi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the icie bit is set. this can be avoided if the in put capture function i is disa bled by reading the icihr (see note 1). 6 the tof bit can be used with interrupt generation in order to measure events that go beyond the timer range (ffffh). figure 41. input capture block diagram figure 42. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit 2 16-bit ic1r register edge detect circuit 1 pin pin ic2r register ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: the rising edge is the active edge.
st72324bxx on-chip peripherals 81/193 output compare in this section, the index, i , may be 1 or 2 because there are two output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output compare register and the free running counter, the output compare function: ? assigns pins with a programmable value if the oc i e bit is set ? sets a flag in the status register ? generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and witable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: (f cpu /cc[1:0]). procedure to use the output compare function, select the following in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. select the timer clock (cc[1:0]) (see ta bl e 5 0 ). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ocf i bit is set the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset) a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits; see ta b l e 5 0 ) table 45. output compare byte distribution register ms byte ls byte ocir oc i hr oc i lr oc i r = t * f cpu presc
on-chip peripherals st72324bxx 82/193 if the timer clock is an external clock, the formula is: where: t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (that is, clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to prevent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). note: 1 after a processor write cycle to the ocihr r egister, the output compar e function is inhibited until the ocilr regist er is also written. 2 if the ocie bit is not set, the ocmpi pin is a general i/o port and the olvli bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3 in both internal and external clock modes, ocfi and ocmpi are set while the counter value equals the ocir register value (see figure 44 on page 83 for an example with f cpu /2 and figure 45 on page 83 for an example with f cpu /4). this behavior is the same in opm or pwm mode. 4 the output compare functions can be used both for generating external events on the ocmpi pins even if the input capture mode is also used. 5 the value in the 16-bit oc i r register and the olvi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. forced output compare capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit = 1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. the folvl i bits have no effect in both one pulse mode and pwm mode. oc i r = t * f ext
st72324bxx on-chip peripherals 83/193 figure 43. output compare block diagram figure 44. output compare timing diagram, f timer =f cpu /2 figure 45. output compare timing diagram, f timer =f cpu /4 output compare 16-bit circuit oc1r register 16-bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2folv1 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf output compare flag i (ocf i ) ocmp i pin (olvl i =1)
on-chip peripherals st72324bxx 84/193 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode: 1. load the oc1r register with the value corresponding to the length of the pulse (see the formula below). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then dedicated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see ta bl e 5 0 ). figure 46. one pulse mode cycle then, on a valid event on the icap1 pin, the counter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter
st72324bxx on-chip peripherals 85/193 the oc1r register value required for a specif ic timing application can be calculated using the following formula: where: t = pulse period (in seconds) f cpu = cpu clock frequnency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on the cc[1:0] bits; see ta bl e 5 0 ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 47 ). note: 1 the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3 if olvl1 = olvl2 a continuous sig nal will be seen on the ocmp1 pin. 4 the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5 when one pulse mode is used oc1r is dedic ated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level olvl2 is dedicated to the one pulse mode. figure 47. one pulse mode timing example (1) 1. iedg1 = 1, oc1r = 2ed0h, olvl1 = 0, olvl2 = 1 oc i r value = t * f cpu presc - 5 oc i r = t * f ext - 5 counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 01f8 01f8 2ed3 ic1r
on-chip peripherals st72324bxx 86/193 figure 48. pulse width modulation mode timing example with two output compare functions (1)(2) 1. oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 2. on timers with only one output compare regist er, a fixed frequency pwm si gnal can be generated using the output compare and the counter overflow to define the pulse length. pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r register, and so this functionality ca n not be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values written in the oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). procedure to use pulse width modulation mode: 1. load the oc2r register with the value corresponding to the period of the signal using the formula below. 2. load the oc1r register with the value corresponding to the period of the pulse if (olvl1 = 0 and olvl2 = 1) using the formula in the opposite column. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc1r register. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see ta bl e 5 0 ). counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 fffc fffd fffe 2ed0 2ed1 2ed2
st72324bxx on-chip peripherals 87/193 figure 49. pulse width modulation cycle if olvl1 = 1 and olvl2 = 0, the length of the positive pulse is the difference between the oc2r and oc1r registers. if olvl1 = olvl2, a continuous signal will be seen on the ocmp1 pin. the oc1r register value required for a specif ic timing application can be calculated using the following formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequnency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on the cc[1:0] bits; see ta bl e 5 0 ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 48 ). note: 1 after a write instruction to the ocihr register, the output co mpare function is inhibited until the ocilr register is also written. 2 the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3 the icf1 bit is set by hardware when the c ounter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4 in pwm mode the icap1 pin can not be used to perform input capture because it is disconnected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext - 5
on-chip peripherals st72324bxx 88/193 10.3.4 low power modes 10.3.5 interrupts table 46. effect of low power modes on 16-bit timer mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting unt il halt mode is exited. counting resumes from the previous count when the mcu is woke n up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequently, when the mcu is wok en up by an interrupt with exit from halt mode capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. table 47. 16-bit timer interrupt control/wakeup capability (1) 1. the 16-bit timer interrupt events are connec ted to the same interrupt vector (see section 7: interrupts ). these events generate an interrupt if the corresponding e nable control bit is set and the interrupt mask in the cc register is reset (rim instruction). interrupt event event flag enable cont rol bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie ye s n o input capture 2 event icf2 output compare 1 event (not available in pwm mode) ocf1 ocie output compare 2 event (not available in pwm mode) ocf2 timer overflow event tof toie
st72324bxx on-chip peripherals 89/193 10.3.6 summary of timer modes 10.3.7 16-bit timer registers each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. control register 1 (cr1) m table 48. summary of timer modes mode timer resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) ye s ye s ye s ye s output compare (1 and/or 2) one pulse mode no not recommended (1) 1. see note 4 in one pulse mode on page 84 . no partially (2) 2. see note 5 in one pulse mode on page 84 . pwm mode not recommended (3) 3. see note 4 in pulse width modulation mode on page 86 . no cr1 reset value: 0000 0000 (00h) 76543210 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 r/w r/w r/w r/w r/w r/w r/w r/w table 49. cr1 register description bit name function 7icie input capture interrupt enable 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. 6ocie output compare interrupt enable 0: interrupt is inhibited. 1: a timer interrupt is generated whenever t he ocf1 or ocf2 bit of the sr register is set. 5toie timer overflow interrupt enable 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set.
on-chip peripherals st72324bxx 90/193 control register 2 (cr2) m 4folv2 forced output compare 2 this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. 3folv1 forced output compare 1 this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp 1 pin, if the oc1e bit is set and even if there is no successful comparison. 2olvl2 output level 2 this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r register and ocxe is set in the cr2 register. this value is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. 1iedg1 input edge 1 this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. 0olvl1 output level 1 the olvl1 bit is copied to the ocmp1 pin whenever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. cr2 reset value: 0000 0000 (00h) 76543210 oc1e oc2e opm pwm cc[1:0] iedg2 exedg r/w r/w r/w r/w r/w r/w r/w table 50. cr2 register description bit name function 7ocie output compare 1 pin enable this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output compare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. 6oc2e output compare 2 pin enable this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output compare mode). whatever the val ue of the oc2e bit, the output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. table 49. cr1 register description (continued) bit name function
st72324bxx on-chip peripherals 91/193 control/status register (csr) m 5opm one pulse mode 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is giv en by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. 4pwm pulse width modulation 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r register. 3:2 cc[1:0] clock control the timer clock mode depends on these bits. 00: timer clock = f cpu /4 01: timer clock = f cpu /2 10: timer clock = f cpu /8 11: timer clock = external clock (where available) note: if the external clock pin is not av ailable, programming the external clock configuration stops the counter. 1iedg2 input edge 2 this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. 0 exedg external clock edge this bit determines which type of level transition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. csr reset value: xxxx x0xx (xxh) 76543210 icf1 ocf1 tof icf2 ocf2 timd reserved ro ro ro ro ro r/w - table 51. csr register description bit name function 7icf1 input capture flag 1 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. table 50. cr2 register description (continued) bit name function
on-chip peripherals st72324bxx 92/193 input capture 1 high register (ic1hr) this is an 8-bit register that contains the high part of the counter value (transferred by the input capture 1 event). 6ocf1 output compare flag 1 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. 5tof timer overflow flag 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. 4icf2 input capture flag 2 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. 3ocf2 output compare flag 2 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. 2timd timer disable this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disabled the output functions (ocmp1 and ocmp2 pins) to reduce power consumption. access to the timer registers is still available, allowing the timer configuration to be changed, or the c ounter reset, while it is disabled. 0: timer enabled. 1: timer prescaler, counter and outputs disabled. 1:0 - reserved, must be kept cleared. ic1hr reset value: undefined 76543210 msb lsb ro ro ro ro ro ro ro ro table 51. csr register description (continued) bit name function
st72324bxx on-chip peripherals 93/193 input capture 1 low register (ic1lr) this is an 8-bit register that contains the low part of the counter value (transferred by the input capture 1 event). output compare 1 high register (oc1hr) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) this is an 8-bit register that contains the low part of the value to be compared to the clr register. output compare 2 high register (oc2hr) this is an 8-bit register that contains the high part of the value to be compared to the chr register. ic1lr reset value: undefined 76543210 msb lsb ro ro ro ro ro ro ro ro oc1hr reset value: 1000 0000 (80h) 76543210 msb lsb r/wr/wr/wr/wr/wr/wr/wr/w oc1lr reset value: 0000 0000 (00h) 76543210 msb lsb r/wr/wr/wr/wr/wr/wr/wr/w oc2hr reset value: 1000 0000 (80h) 76543210 msb lsb r/wr/wr/wr/wr/wr/wr/wr/w
on-chip peripherals st72324bxx 94/193 output compare 2 low register (oc2lr) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) this is an 8-bit register that contains the high part of the counter value. oc2lr reset value: 0000 0000 (00h) 76543210 msb lsb r/wr/wr/wr/wr/wr/wr/wr/w chr reset value: 1111 1111 (ffh) 76543210 msb lsb ro ro ro ro ro ro ro ro clr reset value: 1111 1100 (fch) 76543210 msb lsb ro ro ro ro ro ro ro ro achr reset value: 1111 1111 (ffh) 76543210 msb lsb ro ro ro ro ro ro ro ro
st72324bxx on-chip peripherals 95/193 alternate counter low register (aclr) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. input capture 2 high register (ic2hr) this is an 8-bit register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) this is an 8-bit register that contains the low part of the counter value (transferred by the input capture 2 event). aclr reset value: 1111 1100 (fch) 76543210 msb lsb ro ro ro ro ro ro ro ro 1c2hr reset value: undefined 76543210 msb lsb ro ro ro ro ro ro ro ro 1c2lr reset value: undefined 76543210 msb lsb ro ro ro ro ro ro ro ro table 52. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 csr reset value icf1 x ocf1 x tof x icf2 x ocf2 x timd 0 - x - x timer a: 34 timer b: 44 ic1hr reset value msb xxxxxxx lsb x timer a: 35 timer b: 45 ic1lr reset value msb xxxxxxx lsb x
on-chip peripherals st72324bxx 96/193 10.4 serial peripheral interface (spi) 10.4.1 introduction the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves. however, the spi interface can not be a master in a multi-master system. 10.4.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation 6 master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mode fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. timer a: 36 timer b: 46 oc1hr reset value msb 1000000 lsb 0 timer a: 37 timer b: 47 oc1lr reset value msb 0000000 lsb 0 timer a: 3e timer b: 4e oc2hr reset value msb 1000000 lsb 0 timer a: 3f timer b: 4f oc2lr reset value msb 0000000 lsb 0 timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ic2hr reset value msb xxxxxxx lsb x timer a: 3d timer b: 4d ic2lr reset value msb xxxxxxx lsb x table 52. 16-bit timer register map and reset values (continued) address (hex.) register label 76543210
st72324bxx on-chip peripherals 97/193 10.4.3 general description figure 50 shows the serial peripheral interface (spi) block diagram. the spi has three registers: ? spi control register (spicr) ? spi control/status register (spicsr) ? spi data register (spidr) the spi is connected to external devices through four pins: ? miso: master in / slave out data ? mosi: master out / slave in data ? sck: serial clock out by spi masters and input by spi slaves ?ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves individually and to avoid contention on the data lines. slave ss inputs can be driven by standard i/o ports on the master mcu. figure 50. serial peripheral interface block diagram functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 51 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0
on-chip peripherals st72324bxx 98/193 the communication is always initiated by th e master. when the master device transmits data to a slave device via mosi pin, the sl ave device responds by sending data to the master device via the miso pin. this implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node (in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 54 ) but master and slave must be programmed with the same timing mode. figure 51. single master/s ingle slave application slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr register (see figure 53 ). in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ?ss internal must be held high continuously depending on the data/clock timing relationship, there are two cases in slave mode (see figure 52 ): if cpha = 1 (data latched on second clock edge): ?ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by managing the ss function by software (ssm = 1 and ssi = 0 in the in the spicsr register) if cpha = 0 (data latched on first clock edge): ?ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. if ss is not pulled high, a write collision error will occur when the sl ave writes to the shift register (see write collision error (wcol) on page 102 ). 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msb lsb msb lsb not used if ss is managed by software
st72324bxx on-chip peripherals 99/193 figure 52. generic ss timing diagram figure 53. hardware/software slave select management master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). how to operate the spi in master mode to operate the spi in master mode, perform the following steps in order: 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 54 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits. note: mstr and spe bits remain set only if ss is high. caution: if the spicsr register is not written first, the spicr register setting (mstr bit) might not be taken into account. the transmit sequence begins when software writes a byte in the spidr register. byte 1 byte 2 byte 3 mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) 1 0 ss internal ssm bit ssi bi t ss external pin
on-chip peripherals st72324bxx 100/193 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set. 2. a read to the spidr register. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the following actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 54 ). the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in slave select management on page 98 and figure 52 . if cpha = 1, ss must be held low continuously. if cpha = 0, ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and se t the spe bit to enable the spi i/o functions. slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set. 2. a write or a read to the spidr register. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read.
st72324bxx on-chip peripherals 101/193 the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see overrun condition (ovr) on page 102 ). 10.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 54 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 54 shows an spi transfer with the four combinations of the cpha and cpol bits. the diagram may be interpreted as a master or slave timing diagram where the sck, miso and mosi pins are directly connected between the master and the slave device. note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. figure 54. data clock timing diagram (1) 1. this figure should not be used as a replacement for parametric inform ation. refer to the electrical characterist ics chapter. sck msb bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsb miso (from master) mosi (from slave) ss (to slave) capture strobe cpha = 1 miso (from master) mosi ss (to slave) capture strobe cpha = 0 (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) msb bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsb
on-chip peripherals st72324bxx 102/193 10.4.5 error flags master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: ? the modf bit is set and an spi interrupt request is generated if the spie bit is set. ? the spe bit is reset. this blocks all out put from the device and disables the spi peripheral. ? the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr regi ster while the modf bit is set. 2. a write to the spicr register. note: to avoid any conflicts in an ap plication with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the us er to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. overrun condition (ovr) an overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. write collision error (wcol) a write collision occurs when the software trie s to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted and the software write is unsuccessful. write collisions can occur both in master and slave mode. see also slave select management on page 98 . note: a read collision will never occur since the rece ived data byte is placed in a buffer in which access is always synchronous with the mcu operation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). a software sequence clears the wcol bit (see figure 55 ).
st72324bxx on-chip peripherals 103/193 figure 55. clearing the wcol bit (wri te collision flag) software sequence single master systems a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 56 ). the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are connected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with command fields. figure 56. single master/mul tiple slave configuration clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif = 0 wcol = 0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol = 0 read spicsr read spidr result result note: writing to the spidr register instead of reading it does not reset the wcol bit. miso mos i mosi mosi mosi mosi miso miso miso miso ss ss ss ss sck sck sck sck ports slave mcu slave mcu slave mcu slave mcu maste r mcu ss 5v sck
on-chip peripherals st72324bxx 104/193 10.4.6 low power modes using the spi to wake up the mcu from halt mode in slave configuration, the spi is able to wake up the st7 device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to perform an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the st7 from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the st7 enters halt mode. therefore, if slave selection is configured as external (see slave select management on page 98 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 10.4.7 interrupts 10.4.8 spi registers spi control register (spicr) table 53. effect of low power modes on spi mode description wait no effect on spi. spi interrupt events cause the devi ce to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with exit from halt mode capability. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetching). if several data are received before the wakeup event, then an overrun error is generated. this error can be detected after the fetch of the inte rrupt routine that woke up the device. table 54. spi interrupt control/wakeup capability (1) 1. the spi interrupt events are connecte d to the same interrupt vector (see section 7: interrupts ). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). interrupt event event flag enable contro l bit exit from wait exit from halt spi end of transfer event spif spie yes ye s master mode fault event modf no overrun error ovr spicr reset value: 0000 xxxx (0xh) 76543210 spie spe spr2 mstr cpol cpha spr[1:0] r/w r/w r/w r/w r/w r/w r/w
st72324bxx on-chip peripherals 105/193 table 55. spicr register description bit name function 7 spie serial peripheral interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited. 1: an spi interrupt is generated whenever spif = 1, modf = 1 or ovr = 1 in the spicsr register. 6 spe serial peripheral output enable this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss = 0 (see master mode fault (modf) on page 102 ). the spe bit is cleared by reset, so the spi peripheral is not initially connected to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled 5 spr2 divider enable this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set th e baud rate. refer to table 56: spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. 4mstr master mode this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss = 0 (see master mode fault (modf) on page 102 ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are reversed. 3cpol clock polarity this bit is set and cleared by software. this bit determines the idle state of the serial clock. the cpol bit affect s both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note: if cpol is changed at the communic ation byte boundaries, the spi must be disabled by resetting the spe bit. 2cpha clock phase this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cp ol and cpha settings as the master. 1:0 spr[1:0] serial clock frequency these bits are set and cleared by soft ware. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode (see ta b l e 5 6 ). note: these 2 bits have no effect in slave mode. table 56. spi master mode sck frequency serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0
on-chip peripherals st72324bxx 106/193 spi control/status register (spicsr) f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 spicsr reset value: 0000 0000 (00h) 76543210 spif wcol ovr modf reserved sod ssm ssi ro ro ro ro - r/w r/w r/w table 57. spicsr register description bit name function 7 spif serial peripheral data transfer flag this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie = 1 in the sp icr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared 1: data transfer between the device and an external device has been completed. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. 6wcol write collision status this bit is set by hardware when a writ e to the spidr register is done during a transmit sequence. it is cleared by a software sequence (see figure 55 ). 0: no write collision occurred 1: a write collision has been detected. 5ovr spi overrun error this bit is set by hardware when the byte curr ently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see overrun condition (ovr) on page 102 ). an interrupt is generated if spie = 1 in spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected 4modf mode fault flag this bit is set by hardware when the ss pin is pulled low in master mode (see master mode fault (modf) on page 102 ). an spi interrupt can be generated if spie = 1 in the spicsr register. this bit is cleared by a software sequence (an access to the spicr register while mo df = 1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected. 3 - reserved, must be kept cleared. table 56. spi master mode sck frequency (continued) serial clock spr2 spr1 spr0
st72324bxx on-chip peripherals 107/193 spi data i/o register (spidr) the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this regi ster will initiate transmission/ reception of another byte. note: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value located in the buffer and not the content of the shift register (see figure 50 ). 2sod spi output disable this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode). 0: spi output enabled (if spe = 1). 1: spi output disabled. 1 ssm ss management this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see slave select management on page 98 . 0: hardware management (ss managed by external pin). 1: software management (internal ss signal controlled by ssi bit. external ss pin free for general-purpose i/o) . 0ssi ss internal mode this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0: slave selected. 1: slave deselected. spidr reset value: undefined 76543210 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w table 57. spicsr register description (continued) bit name function
on-chip peripherals st72324bxx 108/193 10.5 serial communicat ions interface (sci) 10.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. 10.5.2 main features full duplex, asynchronous communications nrz standard format (mark/space) dual baud rate generator systems independently programmable transmit and receive baud rates up to 500k baud. programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags 2 receiver wakeup modes ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver 4 error detection flags ? overrun error ? noise error ?frame error ? parity error 5 interrupt sources with flags ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected table 58. spi register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0
st72324bxx on-chip peripherals 109/193 parity control ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 10.5.3 general description the interface is externally connected to another device by two pins (see figure 58 ): tdo: transmit data output. when the transmitter and the receiver are disabled, the output pin returns to its i/o port configuration. when the transmitter and/or the receiver are enabled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the frame is complete this interface uses two types of baud rate generator: a conventional type for commonly-used baud rates an extended type with a prescaler offering a very wide range of baud rates even with non-standard osc illator frequencies
on-chip peripherals st72324bxx 110/193 figure 57. sci block diagram wake up unit sr transmit control tdre tc rdrf idle or nf fe pe sci control interrupt cr1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo ( data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie cr2 receiver control
st72324bxx on-chip peripherals 111/193 10.5.4 functional description the block diagram of the serial control interface is shown in figure 57 . it contains six dedicated registers: 2 control registers (scicr1 and scicr2) a status register (scisr) a baud rate register (scibrr) an extended prescaler receiver register (scierpr) an extended prescaler transmitter register (scietpr) refer to the register descriptions in section 10.5.7 for the definitions of each bit. serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 register (see figure 57 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an extra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 58. word length programming bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 start bit stop bit next start bit idle frame bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 start bit stop bit next start bit start bit start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra ?1? data frame start bit extra ?1? data frame next data frame next data frame idle frame break frame
on-chip peripherals st72324bxx 112/193 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out lsb first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 57 ). procedure 1. select the m bit to define the word length. 2. select the desired baud rate using the scibrr and the scietpr registers. 3. set the te bit to assign the tdo pin to the alternate function and to send a idle frame as first transmission. 4. access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: the tdr register is empty. the data transfer is beginning. the next data can be written in the scidr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write instruction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write instruction to the scidr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence.
st72324bxx on-chip peripherals 113/193 break characters setting the sbk bit loads the shi ft register with a br eak character. the break frame length depends on the m bit (see figure 58 ). as long as the sbk bit is set, the sci send br eak frames to the tdo pi n. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a transmission sends an idle frame after the current word. note: resetting and setting the te bit causes the da ta in the tdr register to be lost. therefore, the best time to toggle the te bit is when the tdre bit is set, that is, before writing the next byte in the scidr. receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least significant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) between the internal bus and the received shift register (see figure 57 ). procedure 1. select the m bit to define the word length. 2. select the desired baud rate using the scibrr and the scierpr registers. 3. set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the error flags can be set if a frame error, noise or an overrun error has been detected during reception. clearing the rdrf bit is performed by th e following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci handles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ilie bit is set and the i bit is cleared in the ccr register.
on-chip peripherals st72324bxx 114/193 overrun error an overrun error occurs when a character is received when rdrf has not been reset. data can not be transferred from the sh ift register to the rdr register as long as the rdrf bit is not cleared. when a overrun error occurs: the or bit is set. the rdr content will not be lost. the shift register will be overwritten. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the scisr register followed by a scidr register read operation. noise error oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the nf flag is set. in the case of start bit detection, the nf flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). therefore, to prevent the nf flag from being set during start bit reception, there should be a valid edge detection as well as three valid samples. when noise is detected in a frame: the nf flag is set at the rising edge of the rdrf bit. data is transferred from the shift register to the scidr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf flag is reset by a scisr register read operation followed by a scidr register read operation. during reception, if a false start bit is detected (for example, 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. there is no rdrf bit set for this fram e and the nf flag is set internally (not accessible to the user). this nf flag is acce ssible along with the rdrf bit when a next valid frame is received. note: if the application start bit is not long enough to match the above requirements, then the nf flag may get set due to the short start bit. in this case, the nf flag may be ignored by the application software when the first valid byte is received. see also noise error causes on page 119 .
st72324bxx on-chip peripherals 115/193 figure 59. sci baud rate and extended prescaler block diagram framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise. a break is received. when the framing error is detected: the fe bit is set by hardware data is transferred from the shift register to the scidr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read operation followed by a scidr register read operation. transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register
on-chip peripherals st72324bxx 116/193 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the sci baud rate register (scibrr) on page 125 . example: if f cpu is 8 mhz (normal mode) and if pr = 13 and tr = rr = 1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is enabled. extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. the extended baud rate generator block diagram is described in figure 59 . the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. the extended prescaler is activated by setting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1,..,255, see sci extended transmit prescaler division register (scietpr) on page 126 . erpr = 1,.. 255, see sci extended receive prescaler division register (scierpr) on page 125 . tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu
st72324bxx on-chip peripherals 117/193 receiver muting and wakeup feature in multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non-addressed receivers. the non-addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits cannot be set. all the receive interrupts are inhibited. a muted receiver may be awakened by one of the following two ways: by idle line detection if the wake bit is reset, by address mark detection if the wake bit is set. a receiver wakes up by idle line detection when the receive line has recognized an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. a receiver wakes up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. caution: in mute mode, do not write to the scicr2 register. if the sci is in mute mode during the read operation (rwu = 1) and an address mark wakeup event occurs (rwu is reset) before the write operation, the rwu bi t will be set again by this writ e operation. co nsequently the address byte is lost and the sci is not woken up from mute mode. parity control parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in ta bl e 5 9 . table 59. frame formats (1)(2) 1. sb = start bit, stb = stop bit, and pb = parity bit. 2. in case of wakeup by an address mark, the msb bit of the data is taken into account and not the parity bit. m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb |
on-chip peripherals st72324bxx 118/193 even parity the parity bit is calculated to obtain an even number of ?1?s inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit, for example, data = 00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity the parity bit is calculated to obtain an odd number of ?1?s inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit, for example, data = 00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode if the pce bit is set then the interface checks if the received data byte has an even number of ?1?s if even parity is selected (ps = 0) or an odd number of ?1?s if odd parity is selected (ps = 1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is generated if pie is set in the scicr1 register. sci clock tolerance during reception, each bit is sampled 16 times. the majority of the 8th, 9th and 10th samples is considered as the bit value. for a valid bit detection, all the three samples should have the same value otherwise the noise flag (nf) is set. for example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be ?1?, but the noise flag bit is set because the three samples values are not the same. consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. this means the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. note: the internal samp ling clock of the microcontroller sa mples the pin value on every falling edge. therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. for example: if the baud rate is 15.625 kbaud (bit length is 64 s), then the 8th, 9th and 10th samples w ill be at 28 s, 32 s and 36 s respectively (the first sample starting ideally at 0 s). but if the falling edge of the internal clock occurs just before the pin value change s, the samples would then be out of sync by ~4 s. this means the entire bit length must be at least 40s (36 s for the 10th sample + 4 s for synchronization with the internal sampling clock).
st72324bxx on-chip peripherals 119/193 clock deviation causes the causes which contribute to the total deviation are: ?d tra : deviation due to transmitte r error (local oscillator er ror of the transmitter or the transmitter is transmitting at a different baud rate). ?d quant : error due to the baud rate quantization of the receiver. ?d rec : deviation of the local o scillator of the re ceiver: this deviation can occur during the reception of one complete sci message assuming that the deviation has been compensated at the beginning of the message. ?d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the sci clock tolerance: d tra + d quant + d rec + d tcl < 3.75% noise error causes see also the description of noise error in receiver on page 113 . start bit the noise flag (nf) is set during start bit rece ption if one of the follo wing conditio ns occurs: 1. a valid falling edge is not de tected. a falling edge is consider ed to be valid if the three consecutive samples before the falling edge occu rs are detected as ?1? and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ?1?. 2. during sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ?1?. therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag from being set. data bits the noise flag (nf) is set during normal data bit reception if the following condition occurs: during the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. the majority of the 8th, 9th and 10th samples is considered as the bit value. therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the noise flag from being set. figure 60. bit sampling in reception mode rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16
on-chip peripherals st72324bxx 120/193 10.5.5 low power modes 10.5.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 10.5.7 sci registers sci status register (scisr) table 60. effect of low power modes on sci mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/receiving until halt mode is exited. table 61. sci interrupt control/wakeup capability interrupt event event flag enable cont rol bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission complete tc tcie yes no received data ready to be read rdrf rie ye s n o overrun error detected or yes no idle line detected idle ilie yes no parity error pe pie yes no scisr reset value: 1100 0000 (c0h) 76543210 tdre tc rdrf idle or nf fe pe ro ro ro ro ro ro ro ro table 62. scisr register description bit name function 7 tdre transmit data register empty this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register. 1: data is transferred to the shift register. note: data will not be transferred to the shif t register unless the tdre bit is cleared.
st72324bxx on-chip peripherals 121/193 6tc transmission complete this bit is set by hardware when transmission of a frame containing data is complete. an interrupt is generated if tcie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a preamble or a break. 5 rdrf received data ready flag this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interr upt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read 4idle idle line detect this bit is set by hardware when a idle line is detected. an interrupt is generated if the ilie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit is not rese t until the rdrf bit has itself been set (that is, a new idle line occurs). 3or overrun error this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf = 1. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rd r register content is not lost but the shift register is overwritten. 2nf noise flag this bit is set by hardware when noise is detected on a received frame. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it appears at the same time as the rdrf bit which itself generates an interrupt. 1fe framing error this bit is set by hardware when a desynchronization, excessive noise or a break character is detected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it appears at the same time as the rdrf bit which itself generates an interrup t. if the word currently being transferred causes both frame error and overrun error, it is transferred and only the or bit will be set. table 62. scisr register description (continued) bit name function
on-chip peripherals st72324bxx 122/193 sci control register 1 (scicr1) 0pe parity error this bit is set by hardware when a parity erro r occurs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an interrupt is ge nerated if pie = 1 in the scicr1 register. 0: no parity error 1: parity error scicr1 reset value: x000 0000 (x0h) 76543210 r8 t8 scid m wake pce ps pie r/w r/w r/w r/w r/w r/w r/w r/w table 63. scicr1 register description bit name function 7r8 receive data bit 8 this bit is used to store the 9th bit of the received word when m = 1. 6t8 transmit data bit 8 this bit is used to store the 9th bit of the transmitted word when m = 1. 5scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled 4m word length this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note: the m bit must not be modified duri ng a data transfer (both transmission and reception). 3wake wakeup method this bit determines the sci wakeup method, it is set or cleared by software. 0: idle line 1: address mark 2pce parity control enable this bit selects the hardware parity c ontrol (generation and detection). when the parity control is enabled, the computed parity is inserted at the msb position (9th bit if m = 1; 8th bit if m = 0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmission). 0: parity control disabled 1: parity control enabled table 62. scisr register description (continued) bit name function
st72324bxx on-chip peripherals 123/193 sci control register 2 (scicr2) 1ps parity selection this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected after the current byte. 0: even parity 1: odd parity 0pie parity interrupt enable this bit enables the interrupt capability of the hardware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled scicr2 reset value: 0000 0000 (00h) 76543210 tie tcie rie ilie te re rwu sbk r/w r/w r/w r/w r/w r/w r/w r/w table 64. scicr2 register description bit name function 7tie transmitter interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre = 1 in the scisr register. 6tcie transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc = 1 in the scisr register. 5rie receiver interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or = 1 or rdrf = 1 in the scisr register. 4ilie idle line interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle = 1 in the scisr register. table 63. scicr1 register description (continued) bit name function
on-chip peripherals st72324bxx 124/193 sci data register (scidr) this register contains the received or transmitted data character, depending on whether it is read from or written to. the data register performs a double function (r ead and write) since it is composed of two registers, one for transmission (t dr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift register (see figure 57 ). the rdr register provides th e parallel interface between the input shift register and the internal bus (see figure 57 ). 3te transmitter enable this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled notes: - during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. - when te is set there is a 1 bit-ti me delay before the transmission starts. caution: the tdo pin is free for general purpose i/o only when the te and re bits are both cleared (or if te is never set). 2re receiver enable this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit note: before selecting mute mode (setting the rwu bit), the sci must first receive some data, otherwise it cannot function in mute mode with wakeup by idle line detection. 1rwu receiver wakeup this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wakeup sequence is recognized. 0: receiver in active mode 1: receiver in mute mode 0sbk send break this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted. 1: break characters are transmitted. note: if the sbk bit is set to ?1? and then to ?0?, the transmitter will send a break word at the end of the current word. scidr reset value: undefined 76543210 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 r/w r/w r/w r/w r/w r/w r/w r/w table 64. scicr2 register description (continued) bit name function
st72324bxx on-chip peripherals 125/193 sci baud rate register (scibrr) sci extended receive prescaler division register (scierpr) this register is used to set the extended presca ler rate division factor for the receive circuit. scibrr reset value: 0000 0000 (00h) 76543210 scp[1:0] sct[2:0] scr[2:0] r/w r/w r/w table 65. scibrr register description bit name function 7:6 scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges. 00: pr prescaling factor = 1 01: pr prescaling factor = 3 10: pr prescaling factor = 4 11: pr prescaling factor = 13 5:3 sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 and scp0 bits, define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. 000: tr dividing factor = 1 001: tr dividing factor = 2 010: tr dividing factor = 4 011: tr dividing factor = 8 100: tr dividing factor = 16 101: tr dividing factor = 32 110: tr dividing factor = 64 111: tr dividing factor = 128 2:0 scr[2:0] sci receiver rate divisor these 3 bits, in conjunction with the scp[1:0] bits, define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 000: rr dividing factor = 1 001: rr dividing factor = 2 010: rr dividing factor = 4 011: rr dividing factor = 8 100: rr dividing factor = 16 101: rr dividing factor = 32 110: rr dividing factor = 64 111: rr dividing factor = 128 scierpr reset value: 0000 0000 (00h) 76543210 erpr[7:0] r/w
on-chip peripherals st72324bxx 126/193 sci extended transmit prescaler division register (scietpr) this register is used to set the external presca ler rate division factor for the transmit circuit. table 66. scierpr register description bit name function 7:0 erpr[7:0] 8-bit extended receive prescaler register the extended baud rate generator is activated when a value different from 00h is stored in this register. therefor e the clock frequency issued from the 16 divider (see figure 59 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not used after a reset. scietpr reset value: 0000 0000 (00h) 76543210 etpr[7:0] r/w table 67. scietpr register description bit name function 7:0 etpr[7:0] 8-bit extended transmit prescaler register the extended baud rate generator is activated when a value different from 00h is stored in this register. therefor e the clock frequency issued from the 16 divider (see figure 59 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not used after a reset. table 68. baud rate selection symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr) = 128, pr = 13 tr (or rr) = 32, pr = 13 tr (or rr) = 16, pr = 13 tr (or rr) = 8, pr = 13 tr (or rr) = 4, pr = 13 tr (or rr) = 16, pr = 3 tr (or rr) = 2, pr =13 tr (or rr) = 1, pr = 13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erpr) = 35, tr (or rr)= 1, pr = 1 14400 ~14285.71
st72324bxx on-chip peripherals 127/193 table 69. sci register map and reset values address (hex.)register label76543210 0050h scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 0051h scidr reset value msb xxxxxxx lsb x 0052h scibrr reset value scp1 0 scp0 0 sct2 0 sct1 0 sct0 0 scr2 0 scr1 0 scr0 0 0053h scicr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 0054h scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 0055h scierpr reset value msb 0000000 lsb 0 0057h scipetpr reset value msb 0000000 lsb 0
on-chip peripherals st72324bxx 128/193 10.6 10-bit a/d converter (adc) 10.6.1 introduction the on-chip analog-to-digital converter (adc) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 10.6.2 main features 10-bit conversion up to 16 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 61 . figure 61. adc block diagram ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 4 div 4 f adc f cpu d1 d0 adcdrl 0 1 00 0000 ch3 div 2
st72324bxx on-chip peripherals 129/193 10.6.3 functional description the conversion is monotonic, meaning that the result never decreases if the analog input does not increase. if the input voltage (v ain ) is greater than v aref (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low-level voltage reference) then the conversion result in the adcdrh and adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conv ersion is stored in the adcdrh and adcdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and samp ling not being completed in the allotted time. a/d converter configuration the analog input ports must be configured as input, no pull-up, no interrupt. refer to section 9: i/o ports . using these pins as analog inputs does not affect th e ability of the port to be read as a logic input. in the adccsr register: select the cs[3:0] bits to assign the analog channel to convert. starting the conversion in the adccsr register: set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: ? the eoc bit is set by hardware ? the result is in the adcdr registers a read to the adcdrh or a write to any bit of the adccsr register resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll the eoc bit. 2. read the adcdrl register 3. read the adcdrh register. th is clears eoc automatically. note: the data is not latched, so both the low and the high data register must be read before the next conversion is complete. therefore, it is recommended to disable interrupts while reading the conversion result. to read only 8 bits, perform the following steps: 1. poll the eoc bit. 2. read the adcdrh register. th is clears eoc automatically.
on-chip peripherals st72324bxx 130/193 changing the conversion channel the application can change channels during conversion. when software modifies the ch[3:0] bits in the adccsr register, the cu rrent conversion is stopped, the eoc bit is cleared, and the a/d converter starts converting the newly selected channel. 10.6.4 low power modes note: the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed. . 10.6.5 interrupts none. 10.6.6 adc registers adc control/status register (adccsr) table 70. effect of low power modes on adc mode description wait no effect on a/d converter. halt a/d converter disabled. after wakeup from halt mode, the a/d co nverter requires a stabilization time t stab (see section 12: electrical characteristics ) before accurate conversions can be performed. adccsr reset value: 0000 0000 (00h) 76543210 eoc speed adon reserved ch[3:0] ro r/w rw - rw table 71. adccsr regi ster description bit name function 7eoc end of conversion this bit is set by hardware. it is cleared by hardware when software reads the adcdrh register or writes to any bit of the adccsr register. 0: conversion is not complete 1: conversion complete 6 speed adc clock selection this bit is set and cleared by software. 0: f adc = f cpu /4 1: f adc = f cpu /2 5adon a/d converter on this bit is set and cleared by software. 0: disable adc and stop conversion 1: enable adc and start conversion
st72324bxx on-chip peripherals 131/193 adc data register high (adcdrh) 4-reserved , must be kept cleared. 3:0 ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. 0000: channel pin = ain0 0001: channel pin = ain1 0010: channel pin = ain2 0011: channel pin = ain3 0100: channel pin = ain4 0101: channel pin = ain5 0110: channel pin = ain6 0111: channel pin = ain7 1000: channel pin = ain8 1001: channel pin = ain9 1010: channel pin = ain10 1011: channel pin = ain11 1100: channel pin = ain12 1101: channel pin = ain13 1110: channel pin = ain14 1111: channel pin = ain15 note: the number of channels is device dependent. refer to section 2: pin description . adcdrh reset value: 0000 0000 (00h) 76543210 d[9:2] ro table 72. adcdrh register description bit name function 7:0 d[9:2] msb of converted analog value table 71. adccsr register description (continued) bit name function
on-chip peripherals st72324bxx 132/193 adc data register low (adcdrl) adcdrl reset value: 0000 0000 (00h) 76543210 reserved d[1:0] -ro table 73. adcdrl register description bit name function 7:2 - reserved. forced by hardware to 0. 1:0 d[1:0] lsb of converted analog value table 74. adc register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0070h adccsr reset value eoc 0 speed 0 adon 00 ch3 0 ch2 0 ch1 0 ch0 0 0071h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0072h adcdrl reset value 0 0 0 0 0 0 d1 0 d0 0
st72324bxx instruction set 133/193 11 instruction set 11.1 cpu addressing modes the cpu features 17 different addressing modes which can be classified in 7 main groups (see ta b l e 7 5 ). : the cpu instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be divided in two submodes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 75. addressing mode groups addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 table 76. cpu addressing mode overview mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2
instruction set st72324bxx 134/193 11.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. 11.1.2 immediate immediate instructions have two bytes: the first byte contains the opcode and the second byte contains the operand value. relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 table 76. cpu addressing mode overview (continued) table 77. inherent instructions instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles
st72324bxx instruction set 135/193 . 11.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two submodes: direct (short) the address is a byte, thus requiring only one byte after the opcode, but only allows 00 - ff addressing space. direct (long) the address is a word, thus allowing 64 kbyte addressing space, but requires 2 bytes after the opcode. 11.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indexed addressing mode consists of three submodes: indexed (no offset) there is no offset, (no extra byte after the opcode), and it allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requiring only one byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte addressing space and requires 2 bytes after the opcode. 11.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two submodes: table 78. immediate instructions instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
instruction set st72324bxx 136/193 indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. 11.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. i table 79. instructions supporting direct, indexed, indirect and indirect indexed addressing modes instructions function long and short ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/subtractions operations bcp bit compare short only clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump sub-routine
st72324bxx instruction set 137/193 11.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. . the relative addressing mode consists of two submodes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in the memory, the address of which follows the opcode. 11.2 instruction groups the st7 family devices use an instruction set co nsisting of 63 instruct ions. the instructions may be subdivided into 13 main groups as illustra ted in the following table: table 80. relative direct and indirect instructions and functions available relative direct/i ndirect instructions function jrxx conditional jump callr call relative table 81. instruction groups group instructions load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf
instruction set st72324bxx 138/193 using a prebyte the instructions are described with one to four opcodes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable the instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one.
st72324bxx instruction set 139/193 table 82. instruction set overview mnemo description function /example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call sub-routine callr call sub-routine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. int pin = 1 (ext. int pin high) jril jump if ext. int pin = 0 (ext. int pin low) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >=
instruction set st72324bxx 140/193 jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg and zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z table 82. instruction set overview (continued) mnemo description function /example dst src i1 h i0 n z c
st72324bxx electrical characteristics 141/193 12 electrical characteristics 12.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 12.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25c and t a =t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 12.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v. they are given only as design guidelines and are not tested. 12.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 62 . figure 62. pin loading conditions c l st7 pin
electrical characteristics st72324bxx 142/193 12.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 63 . figure 63. pin input voltage 12.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 12.2.1 voltage characteristics v in st7 pin table 83. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 6.5 v v pp - v ss programming voltage 13 v in (1)(2) 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operat ion, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7 k for reset , 10 k for i/os). for the same reason, unused i/o pins must not be directly tied to v dd or v ss . 2. i inj(pin) must never be exceeded. this is implicitly ensured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . for true open-drain pads, there is no positive inject ion current, and the corresponding v in maximum must always be respected. input voltage on true open drain pin v ss - 0.3 to 6.5 input voltage on any other pin v ss - 0.3 to v dd +0.3 | v ddx | and | v ssx | variations between different digital power pins 50 mv |v ssa - v ssx | variations between digital and analog ground pins 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 12.8.3 on page 157 v esd(mm) electrostatic discharge voltage (machine model)
st72324bxx electrical characteristics 143/193 12.2.2 current characteristics 12.2.3 thermal characteristics table 84. current characteristics symbol ratings max value unit i vdd total current into v dd power lines (source) (1) 1. all power (v dd ) and ground (v ss ) lines must always be connect ed to the external supply. 32-pin devices 75 ma 44-pin devices 150 i vss total current out of v ss ground lines (sink) (1) 32-pin devices 75 44-pin devices 150 i io output current sunk by any standard i/o and control pin 20 output current sunk by any high sink i/o pin 40 output current source by any i/os and control pin - 25 i inj(pin) (2)(3) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . for true open-drain pads, there is no positive inject ion current, and the corresponding v in maximum must always be respected. 3. negative injection degrades the analog performance of the device. see note in section 12.13.3: adc accuracy on page 171 . if the current injection limits given in table 106: general characteristics on page 158 are exceeded, general device malfunction may result. injected current on v pp pin 5 injected current on reset pin 5 injected current on os c1 and osc2 pins 5 injected current on rom and 32 kbyte flash devices pb0 pin 5 injected current on 8/16 kbyte flash devices pb0 pin + 5 injected current on any other pin (4)(5) 4. when several inputs are submitted to a current injection, the maximum si inj(pin) is the absolute sum of the positive and negative injected currents (insta ntaneous values). thes e results are based on characterization with si inj(pin) maximum current injection on fo ur i/o port pins of the device. 5. true open drain i/o port pins do not accept positive injection. 5 i inj(pin) (2) total injected current (sum of all i/o and control pins) (4) 25 table 85. thermal characteristics symbol ratings value unit t stg storage temperature range -65 to +150 c t j maximum junction temperature (see section 13.3: therma l characteristics )
electrical characteristics st72324bxx 144/193 12.3 operating conditions figure 64. f cpu max versus v dd note: some temperature ranges are only available with a specific package and memory size. refer to section 14: device configuration and ordering information. warning: do not connect 12 v to v pp before v dd is powered on, as this may damage the device. table 86. operating conditions symbol parameter conditions min max unit f cpu internal clock frequency 0 8 mhz v dd operating voltage (except flash write/erase) 3.8 5.5 v operating voltage for flash write/erase v pp = 11.4 to 12.6 v 4.5 5.5 t a ambient temperature range 1-suffix version 0 70 c 5-suffix version -10 85 6-suffix version -40 85 7-suffix version -40 105 3-suffix version -40 125 f cpu [mhz] supply voltage [v] 8 4 2 1 0 3.5 4.0 4.5 5.5 functionality functionality guaranteed in this area not guaranteed in this area 3.8 6 (unless otherwise specified in the tables of parametric data)
st72324bxx electrical characteristics 145/193 12.4 lvd/avd characteristics 12.4.1 operating c onditions with lvd subject to general operating conditions for t a . 12.4.2 auxiliary voltage detector (avd) thresholds subject to general operating conditions for t a . table 87. operating conditions with lvd symbol parameter conditions min typ max unit v it+(lvd) reset release threshold (v dd rise) vd level = high in option byte 4.0 (1) 4.2 4.5 v vd level = med. in option byte (2) 3.55 (1) 3.75 4.0 (1) vd level = low in option byte (2) 2.95 (1) 3.15 3.35 (1) v it-(lvd) reset generation threshold (v dd fall) vd level = high in option byte 3.8 4.0 4.25 (1) vd level = med. in option byte (2) 3.35 (1) 3.55 3.75 (1) vd level = low in option byte (2) 2.8 (1) 3.0 3.15 (1) v hys(lvd) lvd voltage threshold hysteresis (1) v it+(lvd) -v it-(lvd) 150 200 250 mv vt por v dd rise time (1) flash devices 6s/v 100ms/v 8/16 kbyte rom devices 20ms/v 32 kbyte rom devices ms/v t g(vdd) filtered glitch delay on v dd (1) not detected by the lvd 40 ns 1. data based on characterization results, tested in production for rom devices only. 2. if the medium or low thresholds are selected, the detec tion may occur outside the specified operating voltage range. table 88. avd thresholds symbol parameter conditions min typ max unit v it+(avd) 1 ? 0 avdf flag toggle threshold (v dd rise) vd level = high in option byte 4.4 (1) 4.6 4.9 v vd level = med. in option byte 3.95 (1) 4.15 4.4 (1) vd level = low in option byte 3.4 (1) 3.6 3.8 (1) v it-(avd) 0 ? 1 avdf flag toggle threshold (v dd fall) vd level = high in option byte 4.2 4.4 4.65 (1) vd level = med. in option byte 3.75 (1) 4.0 4.2 (1) vd level = low in option byte 3.2 (1) 3.4 3.6 (1) v hys(avd) avd voltage threshold hysteresis v it+(avd) -v it-(avd) 200 mv v it- voltage drop between avd flag set and lvd reset activated v it-(avd) -v it-(lvd) 450 1. data based on characterization results, tested in production for rom devices only.
electrical characteristics st72324bxx 146/193 12.5 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to obtain the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). 12.5.1 rom current consumption table 89. rom current consumption symbol parameter conditions 32 kbyte rom devices 16/8 kbyte rom devices unit typ max (1) typ max (1) i dd supply current in run mode (2) f osc = 2 mhz, f cpu =1mhz f osc = 4 mhz, f cpu =2mhz f osc = 8 mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 0.55 1.10 2.20 4.38 0.87 1.75 3.5 7.0 0.46 0.93 1.9 3.7 0.69 1.4 2.7 5.5 ma supply current in slow mode (2) f osc = 2 mhz, f cpu = 62.5 khz f osc = 4 mhz, f cpu = 125 khz f osc = 8 mhz, f cpu = 250 khz f osc =16mhz, f cpu = 500 khz 53 100 194 380 87 175 350 700 30 70 150 310 60 120 250 500 a supply current in wait mode (2) f osc = 2 mhz, f cpu =1mhz f osc = 4 mhz, f cpu =2mhz f osc = 8 mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 0.31 0.61 1.22 2.44 0.5 1.0 2.0 4.0 0.22 0.45 0.91 1.82 0.37 0.75 1.5 3 ma supply current in slow wait mode (2) f osc = 2 mhz, f cpu = 62.5 khz f osc = 4 mhz, f cpu = 125 khz f osc = 8 mhz, f cpu = 250 khz f osc =16mhz, f cpu = 500 khz 36 69 133 260 63 125 250 500 20 40 90 190 40 90 180 350 a supply current in halt mode (3) -40 c < t a < +85 c <1 10 <1 10 -40 c < t a < +125 c <1 50 <1 50 supply current in active-halt mode (4) f osc =2mhz f osc =4mhz f osc =8mhz f osc =16mhz 15 28 55 107 20 38 75 200 11 22 43 85 15 30 60 150 1. data based on characterization results, tested in production at v dd max. and f cpu max. 2. measurements are done in the following conditions: - program executed from ram, cpu running with ram access. t he increase in consumption when executing from flash is 50%. - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state - lvd disabled. - clock input (osc1) driv en by external square wave - in slow and slow wait modes, f cpu is based on f osc divided by 32 to obtain the total current consumption of the device, add the clock source ( section 12.6.3 ) and the peripheral power consumption ( section 12.5.4 ). 3. all i/o pins in push-pul l 0 mode (when applicable) with a static value at v dd or v ss (no load), lvd disabled. data based on characterization results, tested in production at v dd max. and f cpu max. 4. data based on characterization results , not tested in production. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or v ss (no load); clock input (osc1) dr iven by external square wave, lv d disabled. to obtain the total current consumption of the device, add the clock source consumption ( section 12.6.3 ).
st72324bxx electrical characteristics 147/193 12.5.2 flash current consumption table 90. flash current consumption symbol parameter conditions 32 kbyte flash 16/8 kbyte flash unit typ max (1) 1. data based on characterization results, tested in production at v dd max. and f cpu max. typ max (1) i dd supply current in run mode (2) 2. measurements are done in the following conditions: - program executed from ram, cpu running with ram access. t he increase in consumption when executing from flash is 50% . - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state - lvd disabled - clock input (osc1) driv en by external square wave - in slow and slow wait modes, f cpu is based on f osc divided by 32 - to obtain the total current consumption of the device, add the clock source ( section 12.6.3 ) and the peripheral power consumption ( section 12.5.4 ). f osc = 2 mhz, f cpu =1mhz f osc = 4 mhz, f cpu =2mhz f osc = 8 mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.3 2.0 3.6 7.1 3.0 5.0 8.0 15.0 1 1.4 2.4 4.4 2.3 3.5 5.3 7.0 ma supply current in slow mode (2) f osc = 2 mhz, f cpu = 62.5 khz f osc = 4 mhz, f cpu = 125 khz f osc = 8 mhz, f cpu = 250 khz f osc =16mhz, f cpu = 500 khz 0.6 0.7 0.8 1.1 2.7 3.0 3.6 4.0 0.48 0.53 0.63 0.80 1 1.1 1.2 1.4 supply current in wait mode (2) f osc = 2 mhz, f cpu =1mhz f osc = 4 mhz, f cpu =2mhz f osc = 8 mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 0.8 1.2 2.0 3.5 3.0 4.0 5.0 7.0 0.6 0.9 1.3 2.3 1.8 2.2 2.6 3.6 supply current in slow wait mode (2) f osc = 2 mhz, f cpu = 62.5 khz f osc = 4 mhz, f cpu = 125 khz f osc = 8 mhz, f cpu = 250 khz f osc =16mhz, f cpu = 500 khz 580 650 770 1050 1200 1300 1800 2000 430 470 530 660 950 1000 1050 1200 a supply current in halt mode (3) 3. all i/o pins in push-pul l 0 mode (when applicable) with a static value at v dd or v ss (no load), lvd disabled. data based on characterization results, tested in production at v dd max. and f cpu max. -40c < t a < +85c <1 10 <1 10 -40c < t a < +125c 5 50 <1 50 supply current in active-halt mode (4) 4. data based on characterization results, not tested in producti on. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or v ss (no load); clock input (osc1) dr iven by external square wave, lv d disabled. to obtain the total current consumption of the device, add the clock source consumption ( section 12.6.3 ). f osc =2mhz f osc =4mhz f osc =8mhz f osc =16mhz 365 380 410 500 475 500 550 650 315 330 360 460 425 450 500 600
electrical characteristics st72324bxx 148/193 12.5.3 supply and clock managers the previous current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to obtain the total device consumption, the two current values must be added (except for halt mode). 12.5.4 on-chip peripherals . table 91. oscillators, pll and lvd current consumption symbol parameter conditions typ max unit i dd(rcint) supply current of internal rc oscillator 625 a i dd(res) supply current of resonator oscillator (1)(2) 1. data based on characterization results done wi th the external components specified in section 12.6.3 , not tested in production. 2. as the oscillator is based on a current source, the cons umption does not depend on the voltage. see section 12.6.3 on page 150 i dd(pll) pll supply current v dd = 5v 360 i dd(lvd) lvd supply current 150 300 table 92. on-chip peripherals current consumption symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current (1) 1. data based on a differential i dd measurement between reset configur ation (timer counter running at f cpu /4) and timer counter stopped (only timd bit set). data valid for one timer. t a = 25 c, f cpu = 4 mhz, v dd = 5.0 v 50 a i dd(spi) spi supply current (2) 2. data based on a differential i dd measurement between reset configurat ion (spi disabled) and a permanent spi master communication at maximum speed (data se nt equal to 55h). this measurement includes the pad toggling consumption. 400 i dd(sci) sci supply current (3) 3. data based on a differential i dd measurement between sci low power state (scid = 1) and a permanent sci data transmit sequence. i dd(adc) adc supply current when converting (4) 4. data based on a differential i dd measurement between reset configuration and continuous a/d conversions.
st72324bxx electrical characteristics 149/193 12.6 clock and timing characteristics subject to general operating conditions for v dd , f cpu , and t a . 12.6.1 general timings 12.6.2 external clock source figure 65. typical application with an external clock source table 93. general timings symbol parameter conditions min typ (1) 1. data based on typical application software. max unit t c(inst) instruction cycle time 2312t cpu f cpu = 8 mhz 250 375 1500 ns t v(it) interrupt reaction time t v(it) = t c(inst) + 10 (2) 2. time measured between interrupt event and interrupt vector fetch. t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 10 22 t cpu f cpu =8mhz 1.25 2.75 s table 94. external clock source symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 65. v dd -1 v dd v v osc1l osc1 input pin low level voltage v ss v ss +1 t w(osc1h) t w(osc1l) osc1 high or low time (1) 1. data based on design simulation and/or technology characteristics, not tested in production. 5 ns t r(osc1) t f(osc1) osc1 rise or fall time (1) 15 i lkg osc1 input leakage current v ss < v in < v dd 1 a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i lkg 90% 10%
electrical characteristics st72324bxx 150/193 12.6.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to t he crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). 8/16 kbyte flash and rom devices table 95. crystal and ceramic resonator oscillators (8/16 kbyte flash and rom devices) symbol parameter conditions min typ max unit f osc oscillator frequency (1) 1. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value. refer to crystal/ceramic re sonator manufacturer for more details. lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 1 >2 >4 >8 2 4 8 16 mhz r f feedback resistor (2) 2. data based on characterization results, not tested in pr oduction. the relatively low value of the rf resistor, offers a good protection against issues resulting fr om use in a humid environment, due to the induced leakage and the bias condition change. however, it is re commended to take this point into account if the microcontroller is used in tough humidity conditions. 20 40 k c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) (3) 3. for c l1 and c l2 it is recommended to use high-q uality ceramic capacitors in the 5 pf to 25 pf range (typ.) designed for high-frequency applications and selected to match th e requirements of the crystal or resonator. c l1 and c l2 , are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the se ries combination of c l1 and c l2 . pcb and mcu pin capacitance must be included when sizing c l1 and c l2 (10 pf can be used as a rough estimate of the combined pin and board capacitance). r s = 200 lp oscillator r s = 200 mp oscillator r s = 200 ms oscillator r s = 100 hs oscillator 22 22 18 15 56 46 33 33 pf i 2 osc2 driving current v dd = 5v, v in =v ss lp oscillator mp oscillator ms oscillator hs oscillator 80 160 310 610 150 250 460 910 a
st72324bxx electrical characteristics 151/193 figure 66. typical application with a crystal or ceramic resonator (8/16 kbyte flash and rom devices) 32 kbyte flash and rom devices table 96. crystal and ceramic resonator oscillators (32 kbyte flash and rom devices) symbol parameter conditions min typ max unit f osc oscillator frequency (1) 1. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small rs value. refer to crystal/ceramic resonator manufacturer for more details. 116mhz r f feedback resistor (2) 2. data based on characterization results, not tested in pr oduction. the relatively low value of the rf resistor, offers a good protection against issues resulting fr om use in a humid environment, due to the induced leakage and the bias condition change. however, it is re commended to take this point into account if the microcontroller is used in tough humidity conditions. 20 40 k c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) (3) 3. for c l1 and c l2 it is recommended to use high-quality ceramic c apacitors in the 5-pf to 25-pf range (typ.) designed for high-frequency applications and selected to match th e requirements of the crystal or resonator. c l1 and c l2 , are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the se ries combination of c l1 and c l2 . pcb and mcu pin capacitance must be included when sizing c l1 and c l2 (10 pf can be used as a rough estimate of the combined pin and board capacitance). f osc = 1 to 2 mhz f osc = 2 to 4 mhz f osc = 4 to 8 mhz f osc = 8 to 16 mhz 20 20 15 15 60 50 35 35 pf i 2 osc2 driving current v dd = 5v, v in =v ss lp oscillator mp oscillator ms oscillator hs oscillator 80 160 310 610 150 250 460 910 a osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors
electrical characteristics st72324bxx 152/193 figure 67. typical application with a crystal or ceramic resonator (32 kbyte flash and rom devices) 12.6.4 rc oscillators figure 68. typical f osc(rcint) vs t a table 97. oscrange selecti on for typical resonators supplier f osc (mhz) typical ceramic resonators (1) 1. resonator characteristics given by the ceramic resonator manufacturer. reference recommended oscrange option bit configuration murata 2 cstcc2m00g56a-r0 mp mode (2) 2. lp mode is not recommended for 2 mhz resonator because the peak to peak amplitude is too small (>0.8 v). for more information on these re sonators, please consult www.murata.com. 4 cstcr4m00g55b-r0 ms mode 8 cstce8m00g52a-r0 hs mode 16 cstce16m0v51a-r0 hs mode osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors power down logic feedback loop linear amplifier v dd /2 ref table 98. rc oscillators symbol parameter conditions min typ max unit f osc (rcint) internal rc oscillator frequency (see figure 68) t a =25 c, v dd =5 v 23.55.6mhz 3 3. 2 3. 4 3. 6 3. 8 4 -45 0 25 70 130 t a (c) f osc(rcint) (mhz) vdd = 5v vdd = 5. 5v
st72324bxx electrical characteristics 153/193 note: to reduce disturbance to the rc oscillator, it is re commended to place decoupling capacitors between v dd and v ss as shown in figure 87 on page 170 . 12.6.5 pll characteristics the user must take the pll jitter into account in the application (for example in serial communication or sampling of high frequency signals). the pll jitter is a periodic effect, which is integrated over several cpu cycles. therefore the longer the period of the application signal, the less it will be impacted by the pll jitter. figure 69 shows the pll jitter integrated on application signals in the range 125 khz to 2 mhz. at frequencies of less than 125 khz, the jitter is negligible. figure 69. integrated pll jitter vs signal frequency (1) 1. measurement conditions: f cpu = 8 mhz 12.7 memory characteristics 12.7.1 ram and hardware registers table 99. pll characteristics symbol parameter conditions min typ max unit f osc pll input frequency range 2 4 mhz f cpu /f cpu instantaneous pll jitter (1) 1. data characterized but not tested f osc = 4 mhz 0.7 2 % 0 0.2 0.4 0.6 0.8 1 1.2 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz application frequency +/-jitter (%) max typ table 100. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware register s (only in halt mode). not tested in production. halt mode (or reset) 1.6 v
electrical characteristics st72324bxx 154/193 12.7.2 flash memory table 101. dual voltage hdflash memory symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. typ max (1) unit f cpu operating frequency read mode 0 8 mhz write/erase mode 1 8 v pp programming voltage (2) 2. v pp must be applied only during the programming or eras ing operation and not permanently for reliability reasons. 4.5 v < v dd < 5.5 v 11.4 12.6 v i dd supply current (3) 3. data based on simulation results, not tested in production. write/erase <10 a i pp v pp current (3) read (v pp = 12 v) 200 a write/erase 30 ma t vpp internal v pp stabilization time 10 s t ret data retention t a = 85 c 40 years t a = 105 c 15 t a = 125 c 7 n rw write erase cycles t a =85 c 100 cycles t a =55 c 1000 cycles t prog t erase programming or erasing temperature range -40 25 85 c
st72324bxx electrical characteristics 155/193 12.8 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 12.8.1 functional electromagn etic susceptibility (ems) based on a simple running application on the product (toggling two leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results given in table 102 on page 156 are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015).
electrical characteristics st72324bxx 156/193 12.8.2 electromagnetic interference (emi) based on a simple application running on the product (toggling two leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the boar d and the loading of each pin. table 102. ems test results symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance 32 kbyte flash or rom device: v dd = 5 v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-2 3b 8 or 16 kbyte rom device: v dd = 5 v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 4a 8 or 16 kbyte flash device: v dd = 5 v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-2 4b v fftb fast transient voltage burst limits to be applied through 100 pf on v dd and v dd pins to induce a functional disturbance v dd = 5 v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-4 4a table 103. emi emissions symbol parameter conditions device/package (1) monitored frequency band max vs [f osc /f cpu ] unit 8/4 mhz 16/8 mhz s emi peak level (2) v dd = 5 v t a = +25 c conforming to sae j 1752/3 8/16 kbyte flash lqfp32 and lqfp44 0.1 mhz to 30 mhz 12 18 dbv 30 mhz to 130 mhz 19 25 130 mhz to 1 ghz 15 22 sae emi level 3 3.5 - 32 kbyte flash lqfp32 and lqfp44 0.1 mhz to 30 mhz 13 14 dbv 30 mhz to 130 mhz 20 25 130 mhz to 1 ghz 16 21 sae emi level 3.0 3.5 - 8/16 kbyte rom lqfp32 and lqfp44 0.1 mhz to 30 mhz 12 15 dbv 30 mhz to 130 mhz 23 26 130 mhz to 1 ghz 15 20 sae emi level 3.0 3.5 - 32 kbyte rom lqfp32 and lqfp44 0.1 mhz to 30 mhz 17 21 dbv 30 mhz to 130 mhz 24 30 130 mhz to 1 ghz 18 23 sae emi level 3.0 3.5 - 1. refer to application note an1709 for data on other package types. 2. not tested in production.
st72324bxx electrical characteristics 157/193 12.8.3 absolute maximum rati ngs (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. static latch-up lu : two complementary static tests are required on 6 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. table 104. absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 2000 v v esd(cdm) electrostatic discharge voltage (charged device model) 750 table 105. electrical sensitivities symbol parameter conditions test specification class lu static latch-up class t a = +25 c t a = +85 c t a = +125 c jesd 78 ii level a
electrical characteristics st72324bxx 158/193 12.9 i/o port pin characteristics 12.9.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. table 106. general characteristics symbol parameter conditions min typ max unit v il input low level voltage (standard voltage devices) (1) 0.3xv dd v v ih input high level voltage (1) 0.7xv dd v hys schmitt trigger voltage hysteresis (2) 0.7 i inj(pin) (3) injected current on i/o pins other than pin pb0 (4) v dd = 5 v 4 ma injected current on rom and 32 kbyte flash devices pin pb0 injected current on 8/16 kbyte flash devices pin pb0 0+4 i inj(pin) (3) total injected current (sum of all i/o and control pins) v dd = 5 v 25 ma i lkg input leakage current v ss < v in < v dd 1 a i s static current consumption induced by each floating input pin floating input mode (5)(6) 200 r pu weak pull-up equivalent resistor (7) v in = v ss, v dd = 5 v 50 120 250 k c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time (1) c l = 50 pf between 10% and 90% 25 ns t r(io)out output low to high level rise time (1) 25 t w(it)in external interrupt pulse time (8) 1t cpu 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switchin g levels. based on characterization results, not tested. 3. when the current limitati on is not possible, the v in maximum must be respected, otherwise refer to the i inj(pin) specification. a positive injection is induced by v in >v dd while a negative inject ion is induced by v in st72324bxx electrical characteristics 159/193 figure 70. unused i/o pins configured as input (1) 1. i/o can be left unconnected if it is configured as output (0 or 1) by the software. this has the advantage of greater emc robustness and lower cost. figure 71. typical i pu vs. v dd with v in = v ss 12.9.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. 10 k unused i/o port st7xxx 10 k unused i/o port st7xxx v dd 0 10 20 30 40 50 60 70 80 90 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) ip u (ua ) ta=140c ta=95c ta=25c ta=-45c table 107. output driving current symbol parameter conditions min max unit v ol (1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 72 ) v dd =5v i io = +5 ma 1.2 v i io = +2 ma 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 73 and figure 75 ) i io = +20 ma t a < 85 c t a >85 c 1.3 1.5 i io = +8 ma 0.6 v oh (2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 74 and figure 77 ) i io = -5 ma, t a < 85 c t a >85 c v dd -1.4 v dd -1.6 i io = -2 ma v dd -0.7 1. the i io current sunk must always respect the absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins do not have v oh .
electrical characteristics st72324bxx 160/193 figure 72. typical v ol at v dd = 5 v (standard ports) figure 73. typical v ol at v dd = 5 v (high-sink ports) figure 74. typical v oh at v dd =5 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.005 0.01 0.015 ii o(a ) vol (v) at vdd=5v ta = 14 0c " ta = 95 c ta = 25 c ta = -45 c 51015 i io (ma) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.01 0.02 0.03 ii o (a ) vol(v) at vdd=5v ta= 140 c ta= 95 c ta= 25 c ta= -45c 10 20 30 i io (ma) 2 2.5 3 3.5 4 4.5 5 5.5 -0.01 -0.008 -0.006 -0.004 -0.002 0 ii o ( a ) vdd-voh (v) at vdd=5v v dd= 5v 140c min v dd= 5v 95c min v dd= 5v 25c min v dd= 5v -45c min -10 -8 -6 -4 -2 0 i io (ma)
st72324bxx electrical characteristics 161/193 figure 75. typical v ol vs. v dd (standard ports) figure 76. typical v ol vs. v dd (high-sink ports) figure 77. typical v oh vs. v dd 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=5ma ta= -4 5c ta= 25c ta= 95c ta= 140 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 2 2.5 3 3.5 44.5 55.5 6 vdd(v) vol(v) at iio=2ma ta=-45c ta=25c ta=95c ta=140c 0 0.1 0.2 0.3 0.4 0.5 0.6 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=8ma ta= 140c ta=95c ta=25c ta=-45c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=20ma ta= 140c ta = 95 c ta = 25 c ta=-45c 0 1 2 3 4 5 6 22.533.544.555.56 vdd(v) vdd-voh(v) at iio=-5m a ta= -45c ta= 25c ta= 95c ta= 140c 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vdd-voh(v) at iio=-2ma ta= -45c ta= 25c ta= 95c ta= 140c
electrical characteristics st72324bxx 162/193 12.10 control pin characteristics 12.10.1 asynchronous reset pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. table 108. asynchronous reset pin symbol parameter conditions min typ max unit v il input low level voltage (1) 0.3xv dd v v ih input high level voltage (1) 0.7xv dd v hys schmitt trigger voltage hysteresis (2) 2.5 v ol output low level voltage (3) v dd = 5 v, i io = +2 ma 0.2 0.5 v i io driving current on reset pin 2 ma r on weak pull-up equivalent resistor v dd = 5v 20 30 120 k t w(rstl)out generated reset pulse duration internal reset sources 20 30 42 (4) s t h(rstl)in external reset pulse hold time (5) 2.5 s t g(rstl)in filtered glitch duration (6) 200 ns 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switching levels. 3. the i io current sunk must always respect the absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 4. data guaranteed by design, not tested in production. 5. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on the reset pin with a duration below t h(rstl)in can be ignored. 6. the reset network (the resistor and two capacitors) protec ts the device against parasitic resets, especially in noisy environments.
st72324bxx electrical characteristics 163/193 reset pin protection when lvd is enabled when the lvd is enabled, it is recommended to protect the reset pin as shown in figure 78 and follow these guidelines: 1. the reset network protects the device against parasitic resets. 2. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). 3. whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 12.10.1 . otherwise the reset will not be taken into account internally. 4. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-up for example) is less than the absolute maximum value specified for i inj(reset) in section 12.2.2 on page 143 . 5. when the lvd is enabled, it is mandatory not to connect a pull-up resistor. a 10nf pull- down capacitor is recommended to filter noise on the reset line. 6. in case a capacitive power supply is used, it is recommended to connect a 1m ohm pull-down resistor to the reset pin to discharge any residual voltage induced by this capacitive power supply (this will add 5 a to the power consumption of the mcu). tips when using the lvd: check that all recommendations related to reset circuit have been applied (see section above) check that the power supply is properly decoupled (100 nf + 10 f close to the mcu). refer to an1709. if this cannot be done, it is recommended to put a 100 nf + 1 m ohm pull-down on the reset pin. the capacitors connected on the reset pin and also the power supply are key to avoiding any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. othe rwise: replace 10 nf pull-down on the reset pin with a 5 f to 20 f capacitor. figure 78. reset pin protection when lvd is enabled 0.01 f st72xxx pulse filter r on v dd watchdog lvd rese t internal reset reset external recommended 1 m optional generator (note 6)
electrical characteristics st72324bxx 164/193 reset pin protection when lvd is disabled when the lvd is disabled, it is recommended to protect the reset pin as shown in figure 79 and follow these guidelines: 1. the reset network protects the device against parasitic resets. 2. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). 3. whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 12.10.1 . otherwise the reset will not be taken into account internally. 4. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-up for example) is less than the absolute maximum value specified for i inj(reset) in section 12.2.2 on page 143 . figure 79. reset pin protection when lvd is disabled 0.01f external reset circuit user required st72xxx pulse generator filter r on v dd watchdog internal reset v dd 4.7k
st72324bxx electrical characteristics 165/193 12.10.2 iccsel/v pp pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 80. two typical applications with iccsel/v pp pin (1) 1. when icc mode is not required by the application iccsel/v pp pin must be tied to v ss . 12.11 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). data based on design simulation and/or characterization results, not tested in production. 12.11.1 16-bit timer table 109. iccsel/v pp pin symbol parameter conditions min max unit v il input low level voltage (1) 1. data based on design simulation and/or technology characteristics, not tested in production. flash versions v ss 0.2 v rom versions v ss 0.3 x v dd v ih input high level voltage (1) flash versions v dd - 0.1 12.6 rom versions 0.7 x v dd v dd i lkg input leakage current v in = v ss 1 a iccsel/v pp st72xxx 10k programming tool v pp st72xxx table 110. 16-bit timer symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu = 8 mhz 250 ns f ext timer external clock frequency 0f cpu /4 mhz f pwm pwm repetition rate res pwm pwm resolution 16 bit
electrical characteristics st72324bxx 166/193 12.12 communication interface characteristics 12.12.1 serial peripher al interface (spi) the following characteristics are ubject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. the data is based on design simulation and/or characterization results, not tested in production. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate functi on capability released. in this case, the pin status depends on the i/o port configuration. refer to the i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). table 111. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu = 8 mhz f cpu /128 = 0.0625 f cpu /4 = 2 mhz slave f cpu = 8 mhz 0 f cpu /2 = 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) (1) ss setup time (2) slave t cpu +50 ns t h(ss ) (1) ss hold time slave 120 t w(sckh) (1) t w(sckl) (1) sck high and low time master slave 100 90 t su(mi) (1) t su(si) (1) data input setup time master slave 100 100 t h(mi) (1) t h(si) (1) data input hold time master slave 100 100 t a(so) (1) data output access time slave 0 120 t dis(so) (1) data output disable time slave 240 t v(so) (1) data output valid time slave (after enable edge) 120 t h(so) (1) data output hold time 0 t v(mo) (1) data output valid time master (after enable edge) 120 t h(mo) (1) data output hold time 0 1. data based on design simulation and/or char acterization results, not tested in production. 2. depends on f cpu . for example, if f cpu = 8 mhz, then t cpu = 1 / f cpu = 125 ns and t su(ss) = 175 ns.
st72324bxx electrical characteristics 167/193 figure 81. spi slave timing diagram with cpha = 0 (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, the pin status depends on the i/o port configuration. figure 82. spi slave timing diagram with cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, t he pin status depends on the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit 6 out lsb in lsb out see note 2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit 1 in ss input sck input cpha=1 mosi input miso output cpha=1 t w(sckh) t w(sckl) t a(so) t su(si) t h(si) msb out bit 6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) note 2 t c(sck) hz t v(so) msb in lsb in bit 1 in see note 2 t r(sck) t f(sck)
electrical characteristics st72324bxx 168/193 figure 83. spi master timing diagram (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, the pin status depends on the i/o port configuration. 12.13 10-bit adc characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. ss input sck input cpha = 0 mosi output miso input cpha = 0 cpha = 1 cpha = 1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 seenote2 cpol = 0 cpol = 1 cpol = 0 cpol = 1 t r(sck) t f(sck) t h(mo) t v(mo) table 112. 10-bit adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency 0.4 2 mhz v aref analog reference voltage 0.7*v dd < v aref < v dd 3.8 v dd v v ain conversion voltage range (1) v ssa v aref i lkg input leakage current for analog input (2) -40 c < t a < + 85 c 250 na other t a ranges 1 a r ain external input impedance see figures 84 and 85 k c ain external capacitor on analog input pf f ain variation freq. of analog input signal hz c adc internal sample and hold capacitor 12 pf
st72324bxx electrical characteristics 169/193 figure 84. r ain max. vs f adc with c ain =0 pf (1) 1. c parasitic represents the capacitance of the pcb ( dependent on soldering and pcb layout quality) plus the pad capacitance (3 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. figure 85. recommended c ain and r ain values (1) 1. this graph shows that, depending on the input signal variation (f ain ), c ain can be increased for stabilization time and decreased to allow th e use of a larger serial resistor (r ain) . figure 86. typical a/d converter application t adc conversion time (sample + hold) f cpu = 8 mhz, speed = 0, f adc =2mhz 7.5 s no. of sample capacitor loading cycles no. of hold conversion cycles 4 11 1/f adc 1. any added external serial resistor will downgrade the adc accuracy (espec ially for resistance greater than 10k ). data based on characterization results, not tested in production. 2. injecting negative current on adjacent pins may result in in creased leakage currents. softwar e filtering of the converted analog value is recommended. table 112. 10-bit adc characteristics (continued) symbol parameter conditions min typ max unit 0 5 10 15 20 25 30 35 40 45 0103070 c parasitic (pf) max. r ain (kohm) 2 mhz 1 mhz 0.1 1 10 100 1000 0.01 0.1 1 10 f ain (khz) max. r ain (kohm) cain 10 nf cain 22 nf cain 47 nf c ain ainx st72xxx v dd v t 0.6 v v t 0.6 v c adc 12 pf v ain r ain 10-bit a/d conversion 2 k ( max ) i lkg
electrical characteristics st72324bxx 170/193 12.13.1 analog power supp ly and reference pins depending on the mcu pin count, the package may feature separate v aref and v ssa analog power supply pins. these pins supply power to the a/d converter cell and function as the high and low reference voltages for the conversion. in some packages, v aref and v ssa pins are not available (refer to section 2 on page 15 ). in this case the analog supply and reference pads are internally bonded to the v dd and v ss pins. separation of the digital and analog power pins allow board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see section 12.13.2: general pcb design guidelines ). 12.13.2 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. use separate digital and analog planes. the analog ground plane should be connected to the digital ground plane via a single point on the pcb. filter power to the analog power planes. it is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1f and optionally, if needed 10 pf capacitors as close as possible to the st7 power supply pins and a 1 to 10 f capaci tor close to the power source (see figure 87 ). the analog and digital power supplies should be connected in a star network. do not use a resistor, as v aref is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital outputs on the same i/o port as the a/d input being converted. figure 87. power supply filtering v ss v dd v dd st72xxx v aref v ssa power supply source st7 digital noise filtering external noise filtering 1 to 10 f 0.1 f 0.1 f
st72324bxx electrical characteristics 171/193 12.13.3 adc accuracy figure 88. adc accuracy characteristics table 113. adc accuracy symbol parameter conditions typ max (1) unit rom and 8/16 kbyte flash 32 kbyte flash |e t | total unadjusted error (2) v dd =5 v (2) cpu in run mode @ f adc 2 mhz 34 6 lsb |e o | offset error (2) 23 5 |e g | gain error (2) 0.5 3 4.5 |e d | differential linearity error (2) 12 2 |e l | integral linearity error (2) 3 1. data based on characterization results, monitored in produc tion to guarantee 99.73% within max value from -40c to 125 c ( 3 distribution limits). 2. adc accuracy vs. negative injection current: injecting negativ e current may reduce the accu racy of the conversion being performed on another analog input. any positive inje ction current within the limits specified for i inj(pin) and i inj(pin) in section 12.9 does not affect the adc accuracy. e o e g 1lsb ideal 1lsb ideal v aref v ssa ? 1024 -------------------------------------------- = v in (lsb ideal ) digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1023 (1) (2) e t e d e l (3) v aref v ssa (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) end point correlation line. e t = total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o = offset error: deviation between the first actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum deviation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition and the end point correlation line.
package characteristics st72324bxx 172/193 13 package characteristics 13.1 ecopack in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark. 13.2 package mechanical data 13.2.1 lqfp44 package mechanical data figure 89. 44-pin low profile quad flat package outline table 114. 44-pin low profile quad flat package mechanical data dim. mm inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 a a2 a1 b e l1 l h c e e1 d d1
st72324bxx package characteristics 173/193 13.2.2 sdip42 package mechanical data figure 90. 42-pin plastic dual in-line package, shrink 600-mil width e1 10.00 0.3937 e 0.80 0.0315 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n44 1. values in inches are converted from mm and rounded to 4 decimal digits. table 114. 44-pin low profile quad flat package mechanical data (continued) dim. mm inches (1) min typ max min typ max table 115. 42-pin dual in line package mechanical data dim. mm inches (1) min typ max min typ max a 5.08 0.2000 a1 0.51 0.0201 a2 3.05 3.81 4.57 0.1201 0.1500 0.1799 b 0.38 0.46 0.56 0.0150 0.0181 0.0220 b2 0.89 1.02 1.14 0.0350 0.0402 0.0449 c 0.23 0.25 0.38 0.0091 0.0098 0.0150 d 36.58 36.83 37.08 1.4402 1.4500 1.4598 e e1 ea eb e 0.015 gage plane ec eb d e b b2 a2 a1 c l a
package characteristics st72324bxx 174/193 13.2.3 lqfp32 package mechanical data figure 91. 32-pin low profile quad flat package outline e 15.24 16.00 0.6000 0.6299 e1 12.70 13.72 14.48 0.5000 0.5402 0.5701 e1.78 0.0701 ea 15.24 0.6000 eb 18.54 0.7299 ec 1.52 0.0598 l 2.54 3.30 3.56 0.1000 0.1299 0.1402 number of pins n42 1. values in inches are converted from mm and rounded to 4 decimal digits. table 115. 42-pin dual in line package mechanical data dim. mm inches (1) min typ max min typ max table 116. 32-pin low profile quad flat package mechanical data dim. mm inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 h c l l1 b e a1 a2 a e e1 d d1
st72324bxx package characteristics 175/193 13.2.4 sdip32 package mechanical data figure 92. 32-pin plastic dual in-line package, shrink 400-mil width e 9.00 0.3543 e1 7.00 0.2756 e 0.80 0.0315 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n32 1. values in inches are converted from mm and rounded to 4 decimal digits. table 116. 32-pin low profile quad flat package mechanical data (continued) dim. mm inches (1) min typ max min typ max table 117. 32-pin dual in-line package mechanical data dim. mm inches (1) min typ max min typ max a 3.56 3.76 5.08 0.1402 0.1480 0.2000 a1 0.51 0.0201 a2 3.05 3.56 4.57 0.1201 0.1402 0.1799 b 0.36 0.46 0.58 0.0142 0.0181 0.0228 b1 0.76 1.02 1.40 0.0299 0.0402 0.0551 c 0.20 0.25 0.36 0.0079 0.0098 0.0142 d 27.43 28.45 1.0799 1.1201 d b2 b e a a1 a2 l e1 e ec c ea eb
package characteristics st72324bxx 176/193 e 9.91 10.41 11.05 0.3902 0.4098 0.4350 e1 7.62 8.89 9.40 0.3000 0.3500 0.3701 e1.78 0.0701 ea 10.16 0.4000 eb 12.70 0.5000 ec 1.40 0.0551 l 2.54 3.05 3.81 0.1000 0.1201 0.1500 number of pins n42 1. values in inches are converted from mm and rounded to 4 decimal digits. table 117. 32-pin dual in-line package mechanical data (continued) dim. mm inches (1) min typ max min typ max
st72324bxx package characteristics 177/193 13.3 thermal characteristics table 118. thermal characteristics symbol ratings value unit r thja package thermal resistance (junction to ambient): lqfp44 10x10 lqfp32 7x7 dip42 600mil sdip32 200mil 52 70 55 50 c/w p d power dissipation (1) 1. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int +p port where p int is the chip internal power (i dd x v dd ) and p port is the port power dissipati on depending on the ports used in the application. 500 mw t jmax maximum junction temperature (2) 2. the maximum chip-junction temperature is based on technology characteristics. 150 c
device configuration and ordering information st72324bxx 178/193 14 device configuration and ordering information each device is available for production in user programmable versions (flash) as well as in factory coded versions (rom/fastrom). st72324bxx devices are rom versions. st72p324b devices are factory advanced service technique rom (fastrom) versions: they are factory-programmed hdflash devices. flash devices are shipped to customers with a default content (ffh), while rom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer using the option bytes while the rom devices are factory-configured. figure 93. st72324bxx ordering information scheme st72 f 324b k 2 b 5 family st7 microcontroller family memory size 2 = 8 kbytes 4 = 16 kbytes 6 = 32 kbytes package b = dip 1) m = so u = dfn example: no. of pins k = 32 j = 42 or 44 sub-family 324b temperature range 1 = 0 to +70 c 5 = -10 to +85 c 6 = -40 to +85 c 7 = -40 to +105 c 3 = -40 to +125 c for a list of available options (e.g. memory size, package) and orderabl e part numbers or for further information on any aspect of this device, please contact the st sales office nearest to you. version f = flash p = fastrom blank = rom
st72324bxx device configuration and ordering information 179/193 14.1 flash devices 14.1.1 flash configuration 1. depends on device type as defined in table 122: package selection (opt7) on page 181. the option bytes allow the hardware configuration of the microcontroller to be selected. they have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 programming tool). the default content of the flash is fixed to ffh. to program directly the flash devices using icp, flash devices are shipped to customers with the internal rc clock source. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). table 119. flash option bytes static option byte 0 s tatic option byte 1 7 6 5 43210 7 6 543210 wdg res vd reserved fmp_r pkg1 rstc osctype oscrange plloff haltsw 10 10210 default 1 1 1 0 0 1 1 1 see note 1 1 100111 table 120. option byte 0 bit description bit name function opt7 wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode opt6 wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt5 - reserved, must be kept at default value. opt4:3 vd[1:0] voltage detection these option bits enable the voltage detection block (lvd and avd) with a selected threshold for the lvd and avd. 00: selected lvd = highest threshold (v dd ~4v). 01: selected lvd = medium threshold (v dd ~3.5v). 10: selected lvd = lowest threshold (v dd ~3v). 11: lvd and avd off caution: if the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. below 3.8v, device operation is not guaranteed. for details on the avd and lvd threshold levels refer to section 12.4.1 on page 145 . opt2:1 - reserved, must be kept at default value
device configuration and ordering information st72324bxx 180/193 opt0 fmp_r flash memory readout protection readout protection, when selected, provides a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is selected causes the whole user memory to be erased first, afterwhich the device can be reprogrammed. refer to section 4.3.1 on page 24 and the st7 flash programming reference manual for more details. 0: readout protection enabled 1: readout protection disabled table 121. option byte 1 bit description bit name function opt7 pkg1 pin package selection bit this option bit selects the package (see ta b l e 1 2 2 ). note: on the chip, each i/o port has eight pads. pads that are not bonded to external pins are in input pull-up configuration after reset. the configuration of thes e pads must be kept at reset state to avoid added current consumption. opt6 rstc reset clock cycle selection this option bit selects the number of cpu cycles ap plied during the reset phase and when exiting halt mode. for resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: reset phase with 4096 cpu cycles 1: reset phase with 256 cpu cycles opt5:4 osctype[1:0] oscillator type these option bits select the st7 main clock source type. 00: clock source = resonator oscillator 01: reserved 10: clock source = internal rc oscillator 11: clock source = external source opt3:1 oscrange[2:0] oscillator range when the resonator oscillator type is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. when the external clock source is selected, these bits are set to medium power (2 ~ 4 mhz) . 000: typ. frequency range (lp) = 1 ~ 2 mhz 001: typ. frequency range (mp) = 2 ~ 4 mhz 010: typ. frequency range (ms) = 4 ~ 8 mhz 011: typ. frequency range (hs) = 8 ~ 16 mhz table 120. option byte 0 bit description (continued) bit name function
st72324bxx device configuration and ordering information 181/193 14.2 rom devices 14.2.1 transfer of customer code customer code is made up of the rom/fastrom contents and the list of the selected options (if any). the rom/fastrom contents are to be sent with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. complete the appended st72324bxx microcontroller option list on page 182 to communicate the selected options to stmicroelectronics. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. figure 93: st72324bxx ordering information scheme on page 178 serves as a guide for ordering. the stmicroelectroni cs sales organization will be pleased to provide detailed information on contractual points. caution: the readout protection binary value is inverted between rom and flash products. the option byte checksum differs between rom and flash. opt0 pll off pll activation this option bit activates the pll which allows multiplication by two of the main input clock frequency. th e pll must not be used with the internal rc oscillator. the pll is guaranteed only with an input frequency between 2 and 4 mhz. 0: pll x2 enabled 1: pll x2 disabled caution : the pll can be enabled only if the ?oscrange? (opt3:1) bits are configured to ?mp - 2~ 4 mhz?. otherwise, the device functionality is not guaranteed. table 122. package selection (opt7) version selected package pkg1 j lqfp44/sdip42 1 k lqfp32/sdip32 0 table 121. option byte 1 bit description (continued) bit name function
device configuration and ordering information st72324bxx 182/193 st72324bxx microcontroller option list (last update: march 2009) customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . . . . . . . . . . *the rom code name is assigned by stmicroelectronics. rom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/package (check only one option): conditioning (check only one option): power supply range: [ ] 3.8 to 5.5 v temp. range (do not check for die product). special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ " (lqfp32 7 char., other pkg. 10 char. max) authorized characters are letters, digits, '.', '-', '/' and spaces only. clock source selection: [ ] resonator: [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] internal rc [ ] external clock pll [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] high threshold [ ] med. threshold [ ] low threshold reset delay [ ] 256 cycles [ ] 4096 cycles watchdog selection: [ ] software activation [ ] hardware activation watchdog reset on halt: [ ] reset [ ] no reset readout protection: [ ] disabled [ ] enabled date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . caution: the readout protection binary value is inverted bet ween rom and flash products. the option byte check- sum will differ between rom and flash. --------------------------------- rom device: --------------------------------- | ------------------------------------- 32k ------------------------------------- | ------------------------------------- 16k ------------------------------------- | ------------------------------------- 8k ------------------------------------- lqfp32: | [ ] | [ ] | [ ] dip32: | [ ] | [ ] | [ ] lqfp44 : | [ ] | [ ] | [ ] dip42: | [ ] | [ ] | [ ] --------------------------------- die form: --------------------------------- | --------------------------------------- 32k --------------------------------------- | --------------------------------------- 16k --------------------------------------- | -------------------------------------- 8k --------------------------------------- 32-pin: | [ ] | [ ] | [ ] 44-pin: | [ ] | [ ] | [ ] ------------------------------------------------------------------------ packaged product ------------------------------------------------------------------------ | | ----------------------------------------------------- die product (dice tested at 25 c only) ----------------------------------------------------- lqfp: [ ] tape & reel [ ] tray | [ ] tape & reel dip: [ ] tube | [ ] inked wafer | [ ] sawn wafer on sticky foil [ ] 0 c to +70 c [ ] -10 c to +85 c [ ] -40 c to +85 c [ ] -40 c to +105 c [ ] -40 c to +125 c
st72324bxx device configuration and ordering information 183/193 14.3 development tools 14.3.1 introduction development tools for the st7 microcontrollers include a complete range of hardware systems and software tools from stmicroelectronics and third-party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 14.3.2 evaluation tool s and starter kits st offers complete, affordable starter kits and full-featured evaluation boards that allow you to evaluate microcontroller features and quickly start developing st7 applications. starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application. st evaluation boards are open-design, embedded systems, which are developed and documented to serve as references for your application design. they include sample application software to help you demonstrate, learn about and implement your st7?s features. 14.3.3 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assembler-linker toolchain, which are all seamlessly integrated in the st7 integrated development environments in order to facilit ate the debugging and fine-tuning of your application. the cosmic c comp iler is available in a free version that outputs up to 16 kbytes of code. the range of hardware tools includes cost effective st7-dvp3 series emulators. these tools are supported by the st7 toolset from stmicroelectronics, which includes the stvd7 integrated development environment (ide) with high-level language debugger, editor, project manager and integrated programming interface. 14.3.4 programming tools during the development cycle, the st7-dvp3 and st7-emu3 series emulators and the rlink provide in-circuit prog ramming capability for programmi ng the flash microcontroller on your application board. st also provides dedicated a low-cost dedicated in-circuit programmer, the st7-stick, as well as st7 socket boards which provide all the sockets required for programming any of the devices in a specific st7 subfamily on a platform that can be used with any tool with in- circuit programming capability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment. for additional ordering codes for spare parts, accessories and tools available for the st7 (including from third party manufacturers), refer to the online product selector at www.st.com/mcu.
device configuration and ordering information st72324bxx 184/193 14.3.5 socket and emulator adapter information for information on the type of socket that is supplied with the emulator, refer to the suggested list of sockets in ta b l e 1 2 4 . note: before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device. for footprint and other mechanical information about these sockets and adapters, refer to the manufacturer?s datasheet (www.yamaichi.de for lqfp44 10x10 and www.ironwoodelectronics.com for lqfp32 7x7). 14.4 st7 application notes all relevant st7 application notes can be found on www.st.com. table 123. stmicroelectronics development tools supported products emulation programming st7 dvp3 series st7 emu3 series icc socket board emulator connection kit emulator active probe and teb st72324bj, st72f324bj st7mdt20- dvp3 st7mdt20- t44/dvp st7mdt20j-emu3 st7mdt20j-teb st7sb20j/xx (1) st72324bk, st72f324bk st7mdt20- t32/dvp 1. add suffix /eu, /uk, /us for the power supply of your region. table 124. suggested list of socket types device socket (supplied with st7mdt20j-emu3) emulator adapter (supplied with st7mdt20j-emu3) lqfp32 7x7 ironwood sf-qfe32sa-l-01 ironwood sk-uga06/32a-01 lqfp44 10x10 yamaichi ic149- 044-*52-*5 yamaichi icp-044-5
st72324bxx known limitations 185/193 15 known limitations 15.1 all flash and rom devices 15.1.1 safe connection of osc1/osc2 pins the osc1 and/or osc2 pins must not be left unconnected, otherwise the st7 main oscillator may start and, in this configuration, co uld generate an f osc clock frequency in excess of the allowed maximum (> 16 mhz), putting the st7 in an unsafe/undefined state. refer to section 6.3 on page 32 . 15.1.2 external interrupt missed to avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either ddr and or. any input signal edge during this period will not be detect ed and will not generate an interrupt. this case can typically occur if the application refreshes the port configuration registers at intervals during runtime. workaround the workaround is based on software checking the level on the interrupt pin before and after writing to the pxor or pxddr registers. if there is a level change (depending on the sensitivity programmed for this pin) the interr upt routine is invoked us ing the call instruction with three extra push instructions before executing the interrupt routine (this is to make the call compatible with the iret instruction at the end of the interrupt service routine). but detection of the level change does not make sure that edge occurs during the critical one cycle duration and the interrupt has been mi ssed. this may lead to occurrence of same interrupt twice (one hardware and another with software call). to avoid this, a semaphore is set to ?1? before checking the level change. the semaphore is changed to level '0' inside the interrupt routine. when a level change is detected, the semaphore status is checked and if it is ?1? this means that the last interrupt has been missed. in this case, the interrupt rout ine is invoked with the call instruction. there is another possible case that is, if writing to pxor or pxddr is done with global interrupts disabled (interrupt mask bit set). in this case, the semaphore is changed to ?1? when the level change is detected. detecting a missed interrupt is done after the global interrupts are enabled (interrupt mask bit reset) and by checking the status of the semaphore. if it is ?1? this means that the last interrupt was missed and the interrupt routine is invoked with the call instruction. to implement the workaround, the following software sequence is to be followed for writing into the pxor/pxddr registers. the example is for port pf1 with falling edge interrupt sensitivity. the software sequence is given for both cases (global interrupt disabled/enabled).
known limitations st72324bxx 186/193 case 1: writing to pxor or pxddr wi th global interrupts enabled: ld a,#01 ld sema,a; set the semaphore to '1' ld a,pfdr and a,#02 ld x,a; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a ; write to pfddr ld a,#$ff ld pfor,a ; write to pfor ld a,pfdr and a,#02 ld y,a; store the level after writing to pxor/pxddr ld a,x; check for falling edge cp a,#02 jrne out tnz y jrne out ld a,sema ; check the semaphore status if edge is detected cp a,#01 jrne out call call_routine ; call the interrupt routine out:ld a,#00 ld sema,a .call_routine ; entry to call_routine push a push x push cc .ext1_rt ; entry to interrupt routine ld a,#00 ld sema,a iret case 2: writing to pxor or pxddr with global interrupts disabled: sim ; set the interrupt mask ld a,pfdr and a,#$02 ld x,a ; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a ; write into pfddr ld a,#$ff ld pfor,a ; write to pfor ld a,pfdr and a,#$02 ld y,a ; store the level after writing to pxor/pxddr ld a,x ; check for falling edge cp a,#$02 jrne out tnz y jrne out ld a,#$01 ld sema,a ; set the semaphore to '1' if edge is detected
st72324bxx known limitations 187/193 rim ; reset the interrupt mask ld a,sema ; check the semaphore status cp a,#$01 jrne out call call_routine ; call the interrupt routine rim out:rim jp while_loop .call_routine ; entry to call_routine push a push x push cc .ext1_rt ; entry to interrupt routine ld a,#$00 ld sema,a iret 15.1.3 unexpected reset fetch if an interrupt request occurs while a ?pop cc? instruction is ex ecuted, the interrupt controller does not recognize the source of the interrupt and, by default, passes the reset vector address to the cpu. workaround to solve this issue, a ?pop cc? instruction must always be preceded by a ?sim? instruction. 15.1.4 clearing active interrupts outside interrupt routine when an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur. note: clearing the related interrupt mask will not generate an unwanted reset. concurrent interrupt context the symptom does not occur when the interrupts are handled normally, that is, when: the interrupt flag is cleared within its own interrupt routine the interrupt flag is cleared within any interrupt routine the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following sequence: perform sim and rim operation before and after resetting an active interrupt request. example: ?sim ? reset interrupt flag ?rim
known limitations st72324bxx 188/193 nested interrupt context the symptom does not occur when the interrupts are handled normally, that is, when: the interrupt flag is cleared within its own interrupt routine the interrupt flag is cleared within any interrupt routine with higher or identical priority level the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following sequence: ? push cc ?sim ? reset interrupt flag ?pop cc 15.1.5 16-bit timer pwm mode in pwm mode, the first pwm pulse is missed after writing the value fffch in the oc1r register (oc1hr, oc1lr). it leads to either full or no pwm during a period, depending on the olvl1 and olvl2 settings. 15.1.6 timd set simultaneo usly with oc interrupt if the 16-bit timer is disabled at the same time the output compare event occurs then output compare flag gets locked and cannot be cleared before the timer is enabled again. impact on the application if output compare interrupt is enabled, then the output compare flag cannot be cleared in the timer interrupt routine. consequently the interrupt service routine is called repeatedly. workaround disable the timer interrupt before disabling the timer. again while enabling, first enable the timer then the timer interrupts. perform the following to disable the timer: ? tacr1 or tbcr1 = 0x00h; // disable the compare interrupt ? tacsr i or tbcsr i = 0x40; // disable the timer perform the following to enable the timer again: ? tacsr & or tbcsr & = ~0x4 0; // enable the timer ? tacr1 or tbcr1 = 0x40; // enable the compare interrupt 15.1.7 sci wrong break duration description a single break characte r is sent by setting and resetting the sbk bit in the scicr2 register. in some cases, the break character may have a longer duration than expected: 20 bits instead of 10 bits if m = 0 22 bits instead of 11 bits if m = 1
st72324bxx known limitations 189/193 in the same way, as long as the sbk bit is se t, break characters are sent to the tdo pin. this may lead to generate one break more than expected. occurrence the occurrence of the problem is random and proportional to the baud rate. with a transmit frequency of 19200 baud (f cpu = 8mhz and scibrr = 0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with th e communication protocol in the application, software can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. this can be ensured by temporarily disabling interrupts. the exact sequence is: 1. disable interrupts 2. reset and set te (idle request) 3. set and reset sbk (break request) 4. re-enable interrupts 15.2 8/16 kbyte flash devices only 15.2.1 39-pulse icc entry mode icc mode entry using st7 application clock (3 9 pulses) is not supported. external clock mode must be used (36 pulses). refer to the st7 flash programming reference manua l. 15.2.2 negative current injection on pin pb0 negative current injection on pin pb0 degrades the performance of the device and is not allowed on this pin. 15.3 8/16 kbyte rom devices only 15.3.1 readout prot ection with lvd readout protection is not supported if the lvd is enabled. 15.3.2 i/o port a an d f configuration when using an external quartz crystal or ceramic resonator, a few f osc2 clock periods may be lost when the signal pattern in ta bl e 1 2 5 occurs. this is because this pattern causes the device to enter test mode and return to user mode after a few clock periods. user program execution and i/o status are not changed, only a few clock cycles are lost. this happens with either one of the following configurations pa3 = 0, pf4 = 1, pf1 = 0 while pll option is disabled and pf0 is toggling pa3 = 0, pf4 = 1, pf1 = 0, pf0 = 1 while pll option is enabled this is detailed in ta b l e 1 2 5 .
known limitations st72324bxx 190/193 as a consequence, for cycle-accurate operations, these configurations are prohibited in either input or output mode. workaround to avoid this from occurring, it is recommended to connect one of these pins to gnd (pf4 or pf0) or v dd (pa3 or pf1). table 125. port a and f configuration pll pa3 pf4 pf1 pf0 clock disturbance off010toggling maximum 2 clock cycles lost at each rising or falling edge of pf0 on 0 1 0 1 maximum 1 clock cycle lost out of every 16
st72324bxx revision history 191/193 16 revision history table 126. document revision history date revision changes 05-may-2004 2.0 merged st72f324 flash with st72324b rom datasheet. vt por max modified in section 12.4 on page 145 added figure 79 on page 164 modified v aref min in ?10-bit adc characteristics? on page 168 modified i inj for pb0 in section 12.9 on page 158 added ?clearing active interrupts outside interrupt routine? on page 187 modified ?32k rom devices only? on page 165 30-mar-2005 3 removed clock security system (css) throughout document added notes on st72f324b 8k/16k flash devices in table 27 corrected mco description in section 10.2 on page 69 modified vtpor in section 12.4 on page 145 static current consumption modified in section 12.9 on page 158 updated footnote and figure 78 on page 163 and figure 79 on page 164 modified soldering information in section 13.6 updated section 14 on page 178 added table 27 modified figure 8 on page 25 and note 4 in ?flash program memory? on page 23 added limitation on icc entry mode with 39 pulses to ?known limitations? on page 185 added section 16 on page 166 for st72f324b 8k/16k flash devices modified ?internal sales types on box label? in table 29 on page 157 12-sep-2005 4 removed notes related to st72f324, refer to datasheet rev 3 for specifications on older devices. note: this datasheet rev refers only to st72f324b and st72324b. changed character transmission procedure in section on page 112 updated vt por max in section 12.4 on page 145 updated current consumption for in section 12.5 on page 146 added oscillator diagram and table to section 12.6.3 on page 150 increased data retentio n max. parameter in section 12.7.2 on page 154 updated ordering section 14.3 on page 155 and section 14.5 on page 157 updated development tools section 14.3 on page 183 added ?external interrupt missed? in section 15.1 on page 185 06-feb-2006 5 added description of sicsr register at address 2bh in ta b l e 3 o n page 20 changed description on port pf2 to add internal pull-up in section 9.5.1 on page 63 highlighted note in spi ?master mode operation? on page 99 changed ?static latch-up? on page 157 added note 5 on analog input static current consumption ?general characteristics? on page 158 updated notes in ?thermal characteristics? on page 177
revision history st72324bxx 192/193 10-oct-2007 6 removed references to automotive versions (these are covered by separate st72324b-auto datasheet). changed flash endurance to 1 kcycles at 55c replaced tqfp with lqfp in package outline and device summary on page 1 figure 1 on page 14 : replaced 60 kbytes with 32 kbytes in program memory block replaced tqfp with lqfp in figure 2 on page 15 , in figure 4 on page 16 and in table 2 on page 17 changed note 3 in section 9.2.1 on page 58 changed section 10.1.3 on page 65 changed master mode operation on page 99 added unit of measure to lvd supply current in section 12.5.3 on page 148 replaced tqfp with lqfp in section 12.8.2 on page 156 changed note 4 in section 12.9.1 on page 158 changed figure 78 on page 163 removed emc protective circuitry in figure 79 on page 164 (device works correctly without these components) changed titles of figure 89 on page 172 and figure 91 on page 174 replaced tqfp with lqfp in section 13.3 on page 177 changed section 13.6 on page 171 replaced tqfp with lqfp in section 14.1 on page 179 , in table 122 on page 181 , in section table 122. on page 182 and in section 14.3.5 on page 184 17-mar-2009 7 removed soldering information section. in section 10.6.3: functional description on page 129 , modified ?starting the conversion? paragraph: added ? or a write to any bit of the adccsr register?. modified t ret values in table 101: dual voltage hdflash memory on page 154 . section 13.2: package mechanical data on page 172 modified (values in inches rounded to 4 decimal digits). modified section 12.8.3: absolute maximum ratings (electrica l sensitivity) on page 157 (removed dlu and v esd (mm) ). added section 13.1: ecopack on page 172 . modified ?device configuration and ordering information? on page 178 . table 126. document revision history (continued) date revision changes
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